Logic Synthesis for Low Power VLSI Designs

1. Front Matter

   Pages i-xv

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2. Background, Terminology and, Power Modeling

   1. Front Matter

      Pages 1-1

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   2. Introduction

      • Sasan Iman, Massoud Pedram

      Pages 3-19

   3. Technology Independent Power Analysis and Modeling

      • Sasan Iman, Massoud Pedram

      Pages 21-39

3. Two-level Function Optimization for Low Power

   1. Front Matter

      Pages 41-41

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   2. Two-Level Logic Minimization in CMOS Circuits

      • Sasan Iman, Massoud Pedram

      Pages 43-67

   3. Two-Level Logic Minimization in PLAs

      • Sasan Iman, Massoud Pedram

      Pages 69-84

4. Multi-level Network Optimization for Low Power

   1. Front Matter

      Pages 85-85

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   2. Logic Restructuring for Low Power

      • Sasan Iman, Massoud Pedram

      Pages 87-107

   3. Logic Minimization for Low Power

      • Sasan Iman, Massoud Pedram

      Pages 109-148

   4. Technology Dependent Optimization for Low Power

      • Chi-ying Tsui

      Pages 149-182

   5. Post Mapping Structural Optimization for Low Power

      • Sasan Iman, Massoud Pedram

      Pages 183-195

5. Power Optimization Methodology

   1. Front Matter

      Pages 197-197

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   2. POSE: Power Optimization and Synthesis Environment

      • Sasan Iman, Massoud Pedram

      Pages 199-224

6. Conclusion

   1. Front Matter

      Pages 225-225

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   2. Concluding Remarks

      • Sasan Iman, Massoud Pedram

      Pages 227-232

7. Back Matter

   Pages 233-236

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Logic Synthesis for Low Power VLSI Designs presents a systematic and comprehensive treatment of power modeling and optimization at the logic level. More precisely, this book provides a detailed presentation of methodologies, algorithms and CAD tools for power modeling, estimation and analysis, synthesis and optimization at the logic level. Logic Synthesis for Low Power VLSI Designs contains detailed descriptions of technology-dependent logic transformations and optimizations, technology decomposition and mapping, and post-mapping structural optimization techniques for low power. It also emphasizes the trade-off techniques for two-level and multi-level logic circuits that involve power dissipation and circuit speed, in the hope that the readers can better understand the issues and ways of achieving their power dissipation goal while meeting the timing constraints.
Logic Synthesis for Low Power VLSI Designs is written for VLSI design engineers, CAD professionals, and students who have had a basic knowledge of CMOS digital design and logic synthesis.

• CMOS
• VLSI
• algorithms
• circuit
• computer-aided design (CAD)
• digital design
• logic
• modeling
• network
• optimization

• Escalade Co., University of Southern California, USA

  Sasan Iman

• University of Southern California, USA

  Massoud Pedram

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