CYBER DEAL: 50% Rabatt auf Springer eBooks | Angebot sichern!

cover

ASIC Design and Synthesis

RTL Design Using Verilog

Autoren: Taraate, Vaibbhav

  • Unique to interpretation of ASIC design using Verilog
  • Practical ASIC design scenarios and issues and helpful to professionals
  • More than 150 practical examples for ASIC design, Synthesis and timing analysis
  • Key case studies in the generic form and design synthesis and timing closure for ASIC
Weitere Vorteile

Dieses Buch kaufen

eBook 128,39 €
Preis für Deutschland (Brutto)
  • Die eBook-Version des Titels ist in Kürze verfügbar
  • Erscheinungstermin: 18. Februar 2021
  • ISBN 978-981-334-642-0
  • Versehen mit digitalem Wasserzeichen, DRM-frei
  • Erhältliche Formate:
  • eBooks sind auf allen Endgeräten nutzbar
Hardcover 171,19 €
Preis für Deutschland (Brutto)
Über dieses Buch

This book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution. The book explains how to write efficient RTL using Verilog and how to improve design performance. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies. The contents of this book will be useful to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.

Über die Autor*innen

Vaibbhav Taraate is an entrepreneur and mentor at “1 Rupee S T”. He holds B.E. (Electronics) degree from Shivaji University, Kolhapur (1995) and received a Gold Medal for standing first in all engineering branches. He completed his M.Tech. (Aerospace Control and Guidance) at the Indian Institute of Technology (IIT) Bombay, India, in 1999. He has over 18 years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog , VHDL and SystemVerilog. He has worked with multinational corporations as a consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis and optimization, static timing analysis, system design using microprocessors, high-speed VLSI designs, and architecture design of complex SOCs.


Dieses Buch kaufen

eBook 128,39 €
Preis für Deutschland (Brutto)
  • Die eBook-Version des Titels ist in Kürze verfügbar
  • Erscheinungstermin: 18. Februar 2021
  • ISBN 978-981-334-642-0
  • Versehen mit digitalem Wasserzeichen, DRM-frei
  • Erhältliche Formate:
  • eBooks sind auf allen Endgeräten nutzbar
Hardcover 171,19 €
Preis für Deutschland (Brutto)
Loading...

Wir empfehlen

Loading...

Bibliografische Information

Bibliographic Information
Buchtitel
ASIC Design and Synthesis
Buchuntertitel
RTL Design Using Verilog
Autoren
Copyright
2021
Verlag
Springer Singapore
Copyright Inhaber
Springer Nature Singapore Pte Ltd.
eBook ISBN
978-981-334-642-0
DOI
10.1007/978-981-33-4642-0
Hardcover ISBN
978-981-334-641-3
Auflage
1
Seitenzahl
XII, 421
Anzahl der Bilder
57 schwarz-weiß Abbildungen, 172 Abbildungen in Farbe
Themen