VLSI Physical Design: From Graph Partitioning to Timing Closure

Autoren: Kahng, A.B., Lienig, J., Markov, I.L., Hu, J.

Vorschau
  • Comprehensive coverage of physical design of integrated circuits, PCBs and MCMs, with emphasis on practical algorithms and methodologies
  • A chapter on timing closure that includes a discussion of design flows 
  • Detailed illustrations of key concepts, numerous examples
  • Brief surveys of recent research results with up-to-date references for further reading
  • Accessible to beginners and students
  • Problem sets for students, with solutions
Weitere Vorteile

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Über dieses Lehrbuch

Design and optimization of integrated circuits are essential to the creation of new semiconductor chips, and physical optimizations are becoming more prominent as a result of semiconductor scaling. Modern chip design has become so complex that it is largely performed by specialized software, which is frequently updated to address advances in semiconductor technologies and increased problem complexities. A user of such software needs a high-level understanding of the underlying mathematical models and algorithms. On the other hand, a developer of such software must have a keen understanding of computer science aspects, including algorithmic performance bottlenecks and how various algorithms operate and interact.

"VLSI Physical Design: From Graph Partitioning to Timing Closure"
introduces and compares algorithms that are used during the physical design phase of integrated-circuit design, wherein a geometric chip layout is produced starting from an abstract circuit design. The emphasis is on essential and fundamental techniques, ranging from hypergraph partitioning and circuit placement to timing closure.

Über den Autor

Andrew B. Kahng is Professor of CSE and ECE at UC San Diego, where he holds the endowed chair in High-Performance Computing. He has served as visiting scientist at Cadence (1995-1997) and as founder, chairman and CTO at Blaze DFM (2004-2006).

Jens Lienig is Professor of Electrical Engineering at TU Dresden. He is also the director of the Institute of Electromechanical and Electronic Design at TUD. He has worked as project manager at Tanner Research, Inc. (1996-1999) and Robert Bosch GmbH (1999-2002).

Igor L. Markov is a Professor of Electrical Engineering and Computer Science at the University of Michigan. He has worked at Google (2014-2017) and has been with Facebook since 2018.

Jin Hu was a PhD student at the Computer Science and Engineering (CSE) Division at the University of Michigan. Afterwards, she has been with IBM Corp. (2013-2017) and Bloomberg L.P.


           

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“This book covers the basic algorithms underlying all physical design steps and also shows how they are applied to current instances of the design problems. It will serve the EDA and design community well. It will be a foundational text and reference for the next generation of professionals who will be called on to continue the advancement of our chip design tools.” (Dr. Leon Stok, Vice President, Electronic Design Automation, IBM Corp)

“A clear sign of when a field matures is the availability of a widely accepted textbook. Finally, there is a well-balanced textbook that introduces the key components of a layout synthesis flow with sufficient depth and an eye for the context in which they are used. It lucidly presents what any maker of chip design tools should have as a core foundation.” (Prof. Ralph H.J.M. Otten, Technical University of Eindhoven)

“This is the book I wish I had when I taught EDA in the past, and the one I'm using from now on.” (Dr. Louis K. Scheffer, Howard Hughes Medical Institute)

“I would happily use this book when teaching Physical Design. I know of no other work that's as comprehensive and up-to-date, with algorithmic focus and clear pseudocode for the key algorithms. The book is beautifully designed!” (Prof. John P. Hayes, University of Michigan)

“The entire field of electronic design automation owes the authors a great debt for providing a single coherent source on physical design that is clear and tutorial in nature, while providing details on key state-of-the-art topics such as timing closure.” (Prof. Kurt Keutzer, University of California, Berkeley)

“An excellent balance of the basics and more advanced concepts, presented by top experts in the field.” (Prof. Sachin Sapatnekar, University of Minnesota)

Inhaltsverzeichnis (8 Kapitel)

Inhaltsverzeichnis (8 Kapitel)

Dieses Buch kaufen

eBook 53,49 €
Preis für Deutschland (Brutto)
gültig bis 31. März 2020
  • ISBN 978-90-481-9591-6
  • Versehen mit digitalem Wasserzeichen, DRM-frei
  • Erhältliche Formate: PDF
  • eBooks sind auf allen Endgeräten nutzbar
  • Sofortiger eBook Download nach Kauf
Hardcover 96,29 €
Preis für Deutschland (Brutto)
gültig bis 31. März 2020
  • ISBN 978-90-481-9590-9
  • Kostenfreier Versand für Individualkunden weltweit
  • Gewöhnlich versandfertig in 3-5 Werktagen.
Softcover 69,99 €
Preis für Deutschland (Brutto)
gültig bis 31. März 2020
  • ISBN 978-94-007-9020-9
  • Kostenfreier Versand für Individualkunden weltweit
  • Gewöhnlich versandfertig in 3-5 Werktagen.
eBook Ausleihe  
  • Ausleihdauer: 1 oder 6 Monate
  • kostengünstiger Mietpreis
  • Online-Reader mit Markierungs- und Notizfunktion
  • auf allen Geräten nutzbar
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Bibliografische Information

Bibliographic Information
Buchtitel
VLSI Physical Design: From Graph Partitioning to Timing Closure
Autoren
Copyright
2011
Verlag
Springer Netherlands
Copyright Inhaber
Springer Science+Business Media B.V.
eBook ISBN
978-90-481-9591-6
DOI
10.1007/978-90-481-9591-6
Hardcover ISBN
978-90-481-9590-9
Softcover ISBN
978-94-007-9020-9
Auflage
1
Seitenzahl
XI, 310
Themen