Authors:
- Unique to interpretation of ASIC design using Verilog
- Practical ASIC design scenarios and issues and helpful to professionals
- More than 150 practical examples for ASIC design, Synthesis and timing analysis
- Key case studies in the generic form and design synthesis and timing closure for ASIC
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Table of contents (20 chapters)
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Front Matter
About this book
Authors and Affiliations
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1 Rupee S T, Pune, India
Vaibbhav Taraate
About the author
Bibliographic Information
Book Title: ASIC Design and Synthesis
Book Subtitle: RTL Design Using Verilog
Authors: Vaibbhav Taraate
DOI: https://doi.org/10.1007/978-981-33-4642-0
Publisher: Springer Singapore
eBook Packages: Engineering, Engineering (R0)
Copyright Information: Springer Nature Singapore Pte Ltd. 2021
Hardcover ISBN: 978-981-33-4641-3Published: 07 January 2021
Softcover ISBN: 978-981-33-4644-4Published: 08 January 2022
eBook ISBN: 978-981-33-4642-0Published: 06 January 2021
Edition Number: 1
Number of Pages: XXI, 330
Number of Illustrations: 127 b/w illustrations, 184 illustrations in colour
Topics: Circuits and Systems, Control Structures and Microprogramming, Logic Design