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ASIC/SoC Functional Design Verification

A Comprehensive Guide to Technologies and Methodologies

Authors: Mehta, Ashok B.

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  • Provides readers with a single-source guide to the entire domain of functional design verification
  • Describe many industry standard tools available in the market so readers know which tools to pursue to their greatest advantage
  • Includes complete working Verification Plans of complex SoCs and numerous, real applications to demonstrate each topic introduced
  • Written to be highly accessible and easy to digest
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eBook $119.00
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  • ISBN 978-3-319-59418-7
  • Digitally watermarked, DRM-free
  • Included format: EPUB, PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover $159.99
price for Brazil
  • ISBN 978-3-319-59417-0
  • Free shipping for individuals worldwide
  • Institutional customers should get in touch with their account manager
  • Covid-19 shipping restrictions
  • Usually ready to be dispatched within 3 to 5 business days, if in stock
Softcover $159.99
price for Brazil
  • ISBN 978-3-319-86620-8
  • Free shipping for individuals worldwide
  • Institutional customers should get in touch with their account manager
  • Covid-19 shipping restrictions
  • Usually ready to be dispatched within 3 to 5 business days, if in stock
About this book

This book describes in detail all required technologies and methodologies needed to create a comprehensive, functional design verification strategy and environment to tackle the toughest job of guaranteeing first-pass working silicon.  The author first outlines all of the verification sub-fields at a high level, with just enough depth to allow an engineer to grasp the field before delving into its detail.  He then describes in detail industry standard technologies such as UVM (Universal Verification Methodology), SVA (SystemVerilog Assertions), SFC (SystemVerilog Functional Coverage), CDV (Coverage Driven Verification), Low Power Verification (Unified Power Format UPF), AMS (Analog Mixed Signal) verification, Virtual Platform TLM2.0/ESL (Electronic System Level) methodology, Static Formal Verification, Logic Equivalency Check (LEC), Hardware Acceleration, Hardware Emulation, Hardware/Software Co-verification, Power Performance Area (PPA) analysis on a virtual platform, Reuse Methodology from Algorithm/ESL to RTL, and other overall methodologies.

About the authors

Ashok Mehta has been working in the ASIC/SoC design and verification field for over 20 years. He started his career at Digital Equipment Corporation (DEC) working as a CPU design engineer. He then worked at Data General, Intel (first Pentium Architecture Verification team) and after a route of couple of startups, worked at Applied Micro and currently at TSMC.

He was a very early adopter of Verilog and participated in Verilog, VHDL, iHDL (Intel HDL) and SDF (standard delay format) technical subcommittees. He has also been a proponent of ESL (Electronic System Level) designs. At TSMC he architected and went into production with two industry standard TSMC ESL Reference Flows that take designs from ESL to RTL while preserving the verification environment for reuse from ESL to RTL.

He holds 14 U.S. Patents in the field of SoC and 3DIC design verification.

He is also the author of Second Edition of the book “SystemVerilog Assertions and Functional Coverage – A comprehensive guide to languages, methodologies and applications”. Springer (June 2016).

Ashok earned an MSEE from University of Missouri.

In his spare time, he is an amateur photographer and likes to play drums on 70’s rock music driving his neighbors up the wall J

Table of contents (18 chapters)

Table of contents (18 chapters)

Buy this book

eBook $119.00
price for Brazil
  • ISBN 978-3-319-59418-7
  • Digitally watermarked, DRM-free
  • Included format: EPUB, PDF
  • ebooks can be used on all reading devices
  • Immediate eBook download after purchase
Hardcover $159.99
price for Brazil
  • ISBN 978-3-319-59417-0
  • Free shipping for individuals worldwide
  • Institutional customers should get in touch with their account manager
  • Covid-19 shipping restrictions
  • Usually ready to be dispatched within 3 to 5 business days, if in stock
Softcover $159.99
price for Brazil
  • ISBN 978-3-319-86620-8
  • Free shipping for individuals worldwide
  • Institutional customers should get in touch with their account manager
  • Covid-19 shipping restrictions
  • Usually ready to be dispatched within 3 to 5 business days, if in stock
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Bibliographic Information

Bibliographic Information
Book Title
ASIC/SoC Functional Design Verification
Book Subtitle
A Comprehensive Guide to Technologies and Methodologies
Authors
Copyright
2018
Publisher
Springer International Publishing
Copyright Holder
Springer International Publishing AG
eBook ISBN
978-3-319-59418-7
DOI
10.1007/978-3-319-59418-7
Hardcover ISBN
978-3-319-59417-0
Softcover ISBN
978-3-319-86620-8
Edition Number
1
Number of Pages
XXXI, 328
Number of Illustrations
15 b/w illustrations, 160 illustrations in colour
Topics