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Table of contents (6 chapters)
About this book
This book introduces readers to emerging persistent memory (PM) technologies that promise the performance of dynamic random-access memory (DRAM) with the durability of traditional storage media, such as hard disks and solid-state drives (SSDs). Persistent memories (PMs), such as Intel's Optane DC persistent memories, are commercially available today. Unlike traditional storage devices, PMs can be accessed over a byte-addressable load-store interface with access latency that is comparable to DRAM. Unfortunately, existing hardware and software systems are ill-equipped to fully avail the potential of these byte-addressable memory technologies as they have been designed to access traditional storage media over a block-based interface. Several mechanisms have been explored in the research literature over the past decade to design hardware and software systems that provide high-performance access to PMs.Because PMs are durable, they can retain data across failures, such as power failures andprogram crashes. Upon a failure, recovery mechanisms may inspect PM data, reconstruct state and resume program execution. Correct recovery of data requires that operations to the PM are properly ordered during normal program execution. Memory persistency models define the order in which memory operations are performed at the PM. Much like memory consistency models, memory persistency models may be relaxed to improve application performance. Several proposals have emerged recently to design memory persistency models for hardware and software systems and for high-level programming languages. These proposals differ in several key aspects; they relax PM ordering constraints, introduce varying programmability burden, and introduce differing granularity of failure atomicity for PM operations.This primer provides a detailed overview of the various classes of the memory persistency models, their implementations in hardware, programming languages and software systems proposed in the recent research literature, and the PM ordering techniques employed by modern processors.
Authors and Affiliations
About the authors
Vaibhav Gogte is a Software Engineer at Google. He received his Ph.D. in Computer Science and Engineering fromThe University of Michigan, Ann Arbor in 2020. He received his Master’s in Computer Science and Engineering from The University of Michigan in 2016 and graduated with a Bachelor’s in Electrical and Electronics Engineering from Birla Institute of Technology and Science, Pilani, India in 2011. His research interests are in computer architecture, with a particular focus on architecture, compiler, and systems support for integrating byte-addressable non-volatile memories in future computing systems. His research has been published at several venues, including ISCA, MICRO, ASPLOS, PLDI, and FAST. Aasheesh Kolli is a Software Engineer at Google. His interests are in computer systems architecture; his work includes processor architectures, memory subsystems, programming interfaces, and systems software. His recent research focuses on designing next-generation memory systems, particularly on persistent memory and disaggregated memory systems. Aasheesh received his Ph.D. (2017) and MS (2013) from the University of Michigan, and his BE (2011) from Birla Institute of Technology and Science, Pilani, India. His work has resulted in multiple research papers, including best paper award, at venues like SOSP, ISCA, ASPLOS, and MICRO. He was awarded the 2018 ACM SIGARCH/IEEE CS TCCA Outstanding Dissertation Award. Thomas F. Wenisch is Director of Engineering at Google and an Adjunct Research Scientist (formerly Professor of Computer Science and Engineering) at the University of Michigan, specializing in computer architecture. Wenisch received the NSF CAREER award in 2009, the 2012 University of Michigan Henry Russell Award, a University-wide award for extraordinary accomplishment in scholarship and teaching for early-career faculty, and the Michigan CSE Outstanding Achievement Award for accomplishments in scholarly research, classroom teaching, student mentoring, and leadership in service in 2016. In 2021, Wenisch was awarded the ACM SIGARCH Maurice Wilkes Award, the most prestigious mid-career award in computer architecture, for contributions to memory persistency and energy-efficient systems. He received his Ph.D. in Electrical and Computer Engineering from Carnegie Mellon University
Bibliographic Information
Book Title: A Primer on Memory Persistency
Authors: Vaibhav Gogte, Aasheesh Kolli, Thomas F Wenisch
Series Title: Synthesis Lectures on Computer Architecture
DOI: https://doi.org/10.1007/978-3-031-79205-2
Publisher: Springer Cham
eBook Packages: Synthesis Collection of Technology (R0), eBColl Synthesis Collection 11
Copyright Information: The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Switzerland AG 2022
Softcover ISBN: 978-3-031-79193-2Published: 09 February 2022
eBook ISBN: 978-3-031-79205-2Published: 01 June 2022
Series ISSN: 1935-3235
Series E-ISSN: 1935-3243
Edition Number: 1
Number of Pages: XIX, 95