Overview
- Provides a detailed background on the state of error control methods for on-chip interconnects, including Error Control Coding, Double Sampling, and On-Line Testing
- Describes the use of more complex concatenated codes such as Hamming Product Codes with Type-II HARQ, while emphasizing integration techniques for on-chip interconnect links
- Presents techniques for managing intermittent and permanent errors using a non-interrupting in-line test method with spare wire replacement
- Includes supplementary material: sn.pub/extras
Part of the book series: Integrated Circuits and Systems (ICIR)
Access this book
Tax calculation will be finalised at checkout
Other ways to access
About this book
Similar content being viewed by others
Keywords
Table of contents (11 chapters)
-
3DI Promises and Challenges
-
System and Architecture Design
Editors and Affiliations
Bibliographic Information
Book Title: 3D Integration for NoC-based SoC Architectures
Editors: Abbas Sheibanyrad, Frédéric Pétrot, Axel Jantsch
Series Title: Integrated Circuits and Systems
DOI: https://doi.org/10.1007/978-1-4419-7618-5
Publisher: Springer New York, NY
eBook Packages: Engineering, Engineering (R0)
Copyright Information: Springer Science+Business Media, LLC 2011
Hardcover ISBN: 978-1-4419-7617-8Published: 10 December 2010
Softcover ISBN: 978-1-4614-2748-3Published: 27 December 2012
eBook ISBN: 978-1-4419-7618-5Published: 08 November 2010
Series ISSN: 1558-9412
Series E-ISSN: 1558-9420
Edition Number: 1
Number of Pages: X, 278
Topics: Circuits and Systems, Software Engineering