Test Generation of Crosstalk Delay Faults in VLSI Circuits

1. Front Matter

   Pages i-xi

   PDF

2. Introduction

   • S. Jayanthy, M. C. Bhuvaneswari

   Pages 1-14

3. Delay Fault Testing of VLSI Circuits

   • S. Jayanthy, M. C. Bhuvaneswari

   Pages 15-35

4. Test Generation Algorithms for Crosstalk Faults

   • S. Jayanthy, M. C. Bhuvaneswari

   Pages 37-55

5. An Automatic Test Generation Method for Crosstalk Delay Faults Using Modified FAN Algorithm

   • S. Jayanthy, M. C. Bhuvaneswari

   Pages 57-77

6. ATPG for Crosstalk Delay Faults using Single-Objective Genetic Algorithm

   • S. Jayanthy, M. C. Bhuvaneswari

   Pages 79-97

7. ATPG for Crosstalk Delay Faults Using Particle Swarm Optimization Algorithm

   • S. Jayanthy, M. C. Bhuvaneswari

   Pages 99-108

8. ATPG for Crosstalk Delay Faults Using Multi-objective Genetic Algorithm

   • S. Jayanthy, M. C. Bhuvaneswari

   Pages 109-123

9. Simulation of Asynchronous Sequential Circuits Using Fuzzy Delay Model for Crosstalk Delay Faults

   • S. Jayanthy, M. C. Bhuvaneswari

   Pages 125-139

10. Simulation Based Test Generation for Crosstalk Delay Faults in Asynchronous Sequential Circuits

    • S. Jayanthy, M. C. Bhuvaneswari

    Pages 141-150

11. Summary and Suggestions for Future Research

    • S. Jayanthy, M. C. Bhuvaneswari

    Pages 151-156

This book describes a variety of test generation algorithms for testing crosstalk delay faults in VLSI circuits. It introduces readers to the various crosstalk effects and describes both deterministic and simulation-based methods for testing crosstalk delay faults. The book begins with a focus on currently available crosstalk delay models, test generation algorithms for delay faults and crosstalk delay faults, before moving on to deterministic algorithms and simulation-based algorithms used to test crosstalk delay faults. Given its depth of coverage, the book will be of interest to design engineers and researchers in the field of VLSI Testing.

• Crosstalk delay faults
• Very Large Scale Integration
• Deterministic Algorithms
• Genetic Algorithm
• Fuzzy Delay Model

• Department of Electronics and Communication Engineering, Sri Ramakrishna Engineering College, Coimbatore, India

  S. Jayanthy

• Department of Electrical and Electronics Engineering, PSG College of Technology, Coimbatore, India

  M.C. Bhuvaneswari

Dr. S. Jayanthy is a Professor at the Department of Electronics and Communication Engineering, Sri Ramakrishna Engineering College, Coimbatore, India. She received her Master’s and PhD from PSG College of Technology and Anna University, Chennai respectively. Prof. Jayanthy’s research interests are in VLSI Design & Testing, Genetic Algorithms and Embedded Systems. With more than 20 years of teaching experience, she has published 2 chapters and more than 40 research papers in journals and for national and international conferences and has organized a number of workshops and national conferences in the areas of VLSI, Embedded systems and IOT. She is a life member of Indian Society for Technical Education and Institution of Electronics and Telecommunication Engineers

  
Dr. M.C. Bhuvaneswari is an Associate Professor at the Department of Electrical and Electronics Engineering, PSG College of Technology, Coimbatore, India. She received her BE in Electronics and Communications Engineering from Madras University, and her ME and PhD from Bharathiar University. Her research interests include Applied Electronics, VLSI Design and Testing, Genetic Algorithms, Digital System Design, and Microprocessors. She has published a book on VLSI and Embedded systems (2015) and authored more than 90 research papers in journals and for national and international conferences.  She is a life member of Indian Society for Technical Education, Institute of Engineers (India), Computer Society of India and Systems Society of India. Prof Bhuvaneswari was honored with Dakshinamoorthy award instituted by PSG College of Technology for Teaching Excellence in the year 2010

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