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Advanced HDL Synthesis and SOC Prototyping

RTL Design Using Verilog

  • Book
  • © 2019

Overview

Authors:
  1. Vaibbhav Taraate

    1. 1 Rupee S T (Semiconductor Training @ Rs. 1), Pune, India

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  • Explains System On Chip (SOC) architecture and micro-architecture design and illustration with case studies
  • Explains the ASIC/SOC synthesis and performance improvement techniques
  • Covers practical scenarios and issues, benefiting students and professionals alike
  • Discusses systems design and testing scenarios using modern Field Programmable Gate Arrays (FPGAs)

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Table of contents (16 chapters)

  1. Front Matter

    Pages i-xxi
    Download chapter PDF

  2. Introduction

    • Vaibbhav Taraate
    Pages 1-16

  3. SOC Design

    • Vaibbhav Taraate
    Pages 17-24

  4. RTL Design Guidelines

    • Vaibbhav Taraate
    Pages 25-50

  5. RTL Design and Verification

    • Vaibbhav Taraate
    Pages 51-62

  6. Processor Cores and Architecture Design

    • Vaibbhav Taraate
    Pages 63-95

  7. Buses and Protocols in SOC Designs

    • Vaibbhav Taraate
    Pages 97-117

  8. Memory and Memory Controllers

    • Vaibbhav Taraate
    Pages 119-139

  9. DSP Algorithms and Video Processing

    • Vaibbhav Taraate
    Pages 141-158

  10. ASIC and FPGA Synthesis

    • Vaibbhav Taraate
    Pages 159-172

  11. Static Timing Analysis

    • Vaibbhav Taraate
    Pages 173-196

  12. SOC Prototyping

    • Vaibbhav Taraate
    Pages 197-210

  13. SOC Prototyping Guidelines

    • Vaibbhav Taraate
    Pages 211-230

  14. Design Integration and SOC Synthesis

    • Vaibbhav Taraate
    Pages 231-245

  15. Interconnect Delays and Timing

    • Vaibbhav Taraate
    Pages 247-262

  16. SOC Prototyping and Debug Techniques

    • Vaibbhav Taraate
    Pages 263-276

  17. Testing at the Board Level

    • Vaibbhav Taraate
    Pages 277-290

  18. Back Matter

    Pages 291-307
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Keywords

About this book

This book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks. It covers the complex RTL design scenarios and challenges for SOC designs and provides practical information on performance improvements in SOC, as well as Application Specific Integrated Circuit (ASIC) designs. Prototyping using modern high density Field Programmable Gate Arrays (FPGAs) is discussed in this book with the practical examples and case studies. The book discusses SOC design, performance improvement techniques, testing and system level verification, while also describing the modern Intel FPGA/XILINX FPGA architectures and their use in SOC prototyping. Further, the book covers the Synopsys Design Compiler (DC) and Prime Time (PT) commands, and how they can be used to optimize complex ASIC/SOC designs. The contents of this book will be useful to students and professionals alike.

Authors and Affiliations

  • 1 Rupee S T (Semiconductor Training @ Rs. 1), Pune, India

    Vaibbhav Taraate

About the author

Vaibbhav Taraate is an Entrepreneur and Mentor at “Semiconductor Training @ Rs.1”. He holds a BE (Electronics) degree from Shivaji University, Kolhapur (1995) and received a Gold Medal for standing first in all engineering branches. He completed his M.Tech. (Aerospace Control and Guidance) at the Indian Institute of Technology Bombay (IIT Bombay) in 1999. He has over 15 years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog and VHDL. He has worked with multinational corporations as a consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis/optimization, static timing analysis, system design using microprocessors, high-speed VLSI designs, and architecture design of complex SOCs.

Bibliographic Information

  • Book Title: Advanced HDL Synthesis and SOC Prototyping

  • Book Subtitle: RTL Design Using Verilog

  • Authors: Vaibbhav Taraate

  • DOI: https://doi.org/10.1007/978-981-10-8776-9

  • Publisher: Springer Singapore

  • eBook Packages: Engineering, Engineering (R0)

  • Copyright Information: Springer Nature Singapore Pte Ltd. 2019

  • Hardcover ISBN: 978-981-10-8775-2Published: 18 January 2019

  • eBook ISBN: 978-981-10-8776-9Published: 15 December 2018

  • Edition Number: 1

  • Number of Pages: XXI, 307

  • Number of Illustrations: 67 b/w illustrations, 196 illustrations in colour

  • Topics: Circuits and Systems, Control Structures and Microprogramming, Logic Design

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