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Transactions on High-Performance Embedded Architectures and Compilers V

  • Book
  • © 2019

Overview

Editors:
  1. Per Stenström

    1. Department of Computer Science and Engineering, Chalmers University of Technology, Gothenburg, Sweden

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  2. Cristina Silvano

    1. Politecnico di Milano, Milan, Italy

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  3. Koen Bertels

    1. Delft University of Technology, Delft, The Netherlands

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  4. Michael Schulte

    1. University of Wisconsin–Madison, Madison, USA

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  • Original research on systems targeted at specific computing tasks
  • Of interest to researchers and practitioners designing future embedded systems
  • Covers all aspects of computer architecture, code generation and compiler optimization methods

Part of the book series: Lecture Notes in Computer Science (LNCS, volume 11225)

Part of the book sub series: Transactions on High-Performance Embedded Architectures and Compilers (THIPEAC)

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Table of contents (7 chapters)

  1. Front Matter

    Pages I-IX
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  2. Efficient Mapping of Streaming Applications for Image Processing on Graphics Cards

    • Richard Membarth, Hritam Dutta, Frank Hannig, Jürgen Teich
    Pages 1-20

  3. Programmable and Scalable Architecture for Graphics Processing Units

    • Carlos S. de La Lama, Pekka Jääskeläinen, Heikki Kultala, Jarmo Takala
    Pages 21-38

  4. Circular Buffers with Multiple Overlapping Windows for Cyclic Task Graphs

    • Tjerk Bijlsma, Marco J. G. Bekooij, Gerard J. M. Smit
    Pages 39-58

  5. A Hardware-Accelerated Estimation-Based Power Profiling Unit - Enabling Early Power-Aware Embedded Software Design and On-Chip Power Management

    • Andreas Genser, Christian Bachmann, Christian Steger, Reinhold Weiss, Josef Haid
    Pages 59-78

  6. The Abstract Streaming Machine: Compile-Time Performance Modelling of Stream Programs on Heterogeneous Multiprocessors

    • Paul M. Carpenter, Alex Ramirez, Eduard Ayguade
    Pages 79-99

  7. Prototyping a Configurable Cache/Scratchpad Memory with Virtualized User-Level RDMA Capability

    • George Kalokerinos, Vassilis Papaefstathiou, George Nikiforos, Stamatis Kavadias, Xiaojun Yang, Dionisios Pnevmatikatos et al.
    Pages 100-120

  8. A Dynamic Reconfigurable Super-VLIW Architecture for a Fault Tolerant Nanoscale Design

    • Ricardo Ferreira, Cristoferson Bueno, Marcone Laure, Monica Pereira, Luigi Carro
    Pages 121-139

  9. Back Matter

    Pages 141-141
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Keywords

About this book

Transactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performance embedded computer systems. Recognizing the convergence of embedded and general-purpose computer systems, this journal publishes original research on systems targeted at specific computing tasks as well as systems with broad application bases. The scope of the journal therefore covers all aspects of computer  architecture, code generation and compiler optimization methods of interest to researchers and practitioners designing future embedded systems.


This 5th issue  contains extended versions of papers by the best paper award candidates of IC-SAMOS 2009 and the SAMOS 2009 Workshop, colocated events of the 9th International Symposium on Systems, Architectures, Modeling and Simulation, SAMOS 2009, held in Samos, Greece, in 2009. The 7 papers included in this volume were carefully reviewed and selected. The papers cover research on embedded processor hardware/software design and integration and present challenging research trends.

Editors and Affiliations

  • Department of Computer Science and Engineering, Chalmers University of Technology, Gothenburg, Sweden

    Per Stenström

  • Politecnico di Milano, Milan, Italy

    Cristina Silvano

  • Delft University of Technology, Delft, The Netherlands

    Koen Bertels

  • University of Wisconsin–Madison, Madison, USA

    Michael Schulte

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