VLSI Design and Test

1. Front Matter

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2. Process Aware Ultra-High-Speed Hybrid Sensing Technique for Low Power Near-Threshold SRAM

   • Bhupendra Singh Reniwal, Santosh Kumar Vishvakarma

   Pages 1-9

3. A Novel Design Methodology for High Tuning Linearity and Wide Tuning Range Ring Voltage Controlled Oscillator

   • Gudlavalleti Rajahari, Yashu Anand Varshney, Subash Chandra Bose

   Pages 10-18

4. A Low-Power Wideband High Dynamic Range Single-Stage Variable Gain Amplifier

   • Vivek Verma, Chetan D. Parikh

   Pages 19-25

5. An Ultra-Wideband Baseband Transmitter Design for Wireless Body Area Network

   • R. K. Naga Mahesh, Akash Ganesan, Manchi Pavan Kumar, Roy Paily

   Pages 26-34

6. Computational Functions’ VLSI Implementation for Compressed Sensing

   • Shrirang Korde, Amol Khandare, Raghavendra Deshmukh, Rajendra Patrikar

   Pages 35-43

7. A Novel Input Capacitance Modeling Methodology for Nano-Scale VLSI Standard Cell Library Characterization

   • Akhtar W. Alam, Esakkimuthu Dhakshinamoorthy, Prince Mathew, Narender Ponna

   Pages 44-48

8. An Area Efficient Wide Range On-Chip Delay Measurement Architecture

   • Rahul Krishnamurthy, G. K. Sharma

   Pages 49-58

9. 10 Gbps Current Mode Logic I/O Buffer

   • Akhil Rathore, Chetan D Parikh

   Pages 59-65

10. Kapees: A New Tool for Standard Cell Placement

    • Sameer Pawanekar, Kalpesh Kapoor, Gaurav Trivedi

    Pages 66-73

11. Preemptive Test Scheduling for Network-on-Chip Using Particle Swarm Optimization

    • Kanchan Manna, Shailesh Singh, Santanu Chattopadhyay, Indranil Sengupta

    Pages 74-82

12. Energy Efficient Array Initialization Using Loop Unrolling with Partial Gray Code Sequence

    • Sumanta Pyne, Ajit Pal

    Pages 83-93

13. Design and Simulation of Bulk Micromachined Accelerometer for Avionics Application

    • Amit Sharma, Ravindra Mukhiya, S. Santosh Kumar, B. D. Pant

    Pages 94-99

14. Performance Analysis of Subthreshold 32-Bit Kogge-Stone Adder for Worst-Case-Delay and Power in Sub-micron Technology

    • Himadri Singh Raghav, Sachin Maheshwari, B. Prasad Singh

    Pages 100-107

15. Characterization of Logical Effort for Improved Delay

    • Sachin Maheshwari, Himadri Singh Raghav, Anu Gupta

    Pages 108-117

16. A Dual Material Double-Layer Gate Stack Junctionless Transistor for Enhanced Analog Performance

    • Ratul Kumar Baruah, Roy P. Paily

    Pages 118-127

17. An Improved g _m /I _D Methodology for Ultra-Low-Power Nano-Scale CMOS OTA Design

    • Somnath Paul, Abhijit Dana, Soumya Pandit

    Pages 128-137

18. An Efficient RF Energy Harvester with Tuned Matching Circuit

    • Sachin Agrawal, Sunil Pandey, Jawar Singh, P. N. Kondekar

    Pages 138-145

19. A Modified Gate Replacement Algorithm for Leakage Reduction Using Dual-Tox in CMOS VLSI Circuits

    • Surabhi Singh, Brajesh K. Kaushik, Sudeb Dasgupta

    Pages 146-152

20. Impact of Fin Width and Graded Channel Doping on the Performance of 22nm SOI FinFET

    • Jose Joseph, Rajendra Patrikar

    Pages 153-159

This book constitutes the refereed proceedings of the 17th International Symposium on VLSI Design and Test, VDAT 2013, held in Jaipur, India, in July 2013. The 44 papers presented were carefully reviewed and selected from 162 submissions. The papers discuss the frontiers of design and test of VLSI components, circuits and systems. They are organized in topical sections on VLSI design, testing and verification, embedded systems, emerging technology.

• SRAM arrays
• VLSI
• digital circuits
• multi-processor architectures
• network-on-chip

• MNIT, Jaipur, India

  Manoj Singh Gaur, Vijay Laxmi, Dharmendra Boolchandani

• University of Southampton, UK

  Mark Zwolinski

• IIT Bombay, Mumbai, India

  Virendra Sing

• Auburn University, USA

  Adit D. Sing

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