Reconfigurable Computing: Architectures, Tools and Applications

1. Front Matter

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2. Applications

   1. Heterogeneous Reconfigurable System for Adaptive Particle Filters in Real-Time Applications

      • Thomas C. P. Chau, Xinyu Niu, Alison Eele, Wayne Luk, Peter Y. K. Cheung, Jan Maciejowski

      Pages 1-12

   2. Hardware Acceleration of Genetic Sequence Alignment

      • J. Arram, K. H. Tsoi, Wayne Luk, P. Jiang

      Pages 13-24

   3. An FPGA Acceleration for the Kd-tree Search in Photon Mapping

      • Takuya Kuhara, Takaaki Miyajima, Masato Yoshimi, Hideharu Amano

      Pages 25-36

   4. SEU Resilience of DES, AES and Twofish in SRAM-Based FPGA

      • Uli Kretzschmar, Armando Astarloa, Jesús Lázaro

      Pages 37-46

   5. A Fast Poisson Solver for Hybrid Reconfigurable System

      • Vitor Gomes, Haroldo Campos Velho, Andrea Charão

      Pages 47-58

   6. An Architecture for IPv6 Lookup Using Parallel Index Generation Units

      • Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura

      Pages 59-71

   7. Hardware Index to Set Partition Converter

      • Jon T. Butler, Tsutomu Sasao

      Pages 72-83

   8. Teaching SoC Using Video Games to Improve Student Engagement

      • Christopher J. Martinez

      Pages 84-89

3. Arithmetic

   1. Parameterized Design and Evaluation of Bandwidth Compressor for Floating-Point Data Streams in FPGA-Based Custom Computing

      • Tomohiro Ueno, Yoshiaki Kono, Kentaro Sano, Satoru Yamamoto

      Pages 90-102

   2. Hardware Acceleration of Matrix Multiplication over Small Prime Finite Fields

      • Shane T. Fleming, David B. Thomas

      Pages 103-114

   3. Flexible Design of a Modular Simultaneous Exponentiation Core for Embedded Platforms

      • Geoffrey Ottoy, Bart Preneel, Jean-Pierre Goemaere, Lieven De Strycker

      Pages 115-121

4. Design Optimization for FPGAs

   1. Architecture for Transparent Binary Acceleration of Loops with Memory Accesses

      • Nuno Paulino, João Canas Ferreira, João M. P. Cardoso

      Pages 122-133

   2. Parametric Optimization of Reconfigurable Designs Using Machine Learning

      • Maciej Kurek, Tobias Becker, Wayne Luk

      Pages 134-145

   3. Performance Modeling of Pipelined Linear Algebra Architectures on FPGAs

      • Sam Skalicky, Sonia López, Marcin Łukowiak, James Letendre, Matthew Ryan

      Pages 146-153

5. Architectures

   1. Fast Template-Based Heterogeneous MPSoC Synthesis on FPGA

      • Youenn Corre, Jean-Philippe Diguet, Loïc Lagadec, Dominique Heller, Dominique Blouin

      Pages 154-166

   2. Configurable Fault-Tolerance for a Configurable VLIW Processor

      • Fakhar Anjam, Stephan Wong

      Pages 167-178

   3. Hierarchical and Multiple Switching NoC with Floorplan Based Adaptability

      • Debora Matos, Cezar Reinbrecht, Marcio Kreutz, Gianluca Palermo, Luigi Carro, Altamiro Susin

      Pages 179-184

6. Place and Routing

   1. HTR: On-Chip Hardware Task Relocation for Partially Reconfigurable FPGAs

      • Aurelio Morales-Villanueva, Ann Gordon-Ross

      Pages 185-196

   2. Performance Analysis and Optimization of High Density Tree-Based 3D Multilevel FPGA

      • Vinod Pangracious, Zied Marrakchi, Emna Amouri, Habib Mehrez

      Pages 197-209

This book constitutes the thoroughly refereed conference proceedings of the 9th International Symposium on Reconfigurable Computing: Architectures, Tools and Applications, ARC 2013, held in Los Angeles, CA, USA, in March 2013. The 28 revised papers presented, consisting of 20 full papers and 11 poster papers were carefully selected from 41 submissions. The topics covered are applications, arithmetic, design optimization for FPGAs, architectures, place and routing.

• VLIW processor
• dynamically reconfigurable hardware
• embedded systems
• partially reconfigurable FPGAs
• performance modeling
• algorithm analysis and problem complexity

• Department of Computer Science and Engineering, University of California, Riverside, USA

  Philip Brisk

• Department of Computing, Imperial College, London, UK

  José Gabriel Figueiredo Coutinho

• Departamento de Engenharia Informática, Instituto Superior Técnico/INESC-ID, Porto Salvo, Portugal

  Pedro C. Diniz

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