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High Performance Computing - HiPC 2006

13th International Conference Bangalore, India, December 18-21, 2006, Proceedings

  • Conference proceedings
  • © 2006

Overview

Editors:
  1. Yves Robert

    1.  ,  

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  2. Manish Parashar

    1. Department of Electrical and Computer Engineering, Rutgers, the State University of New Jersey, Piscataway, USA

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  3. Ramamurthy Badrinath

    1. Hewlett-Packard ISO, Sy 192, Bangalore, India

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  4. Viktor K. Prasanna

    1. Department of Electrical Engineering, University of Southern California, Los Angeles, USA

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Part of the book series: Lecture Notes in Computer Science (LNCS, volume 4297)

Part of the book sub series: Theoretical Computer Science and General Issues (LNTCS)

Included in the following conference series:

Conference proceedings info: HiPC 2006.

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Table of contents (59 papers)

  1. Front Matter

    Download chapter PDF

  3. Banquet Speech

    1. Conquering Complexity in Information Systems

      • Harrick Vin
      Pages 8-8

  4. Plenary Session – Best Papers

    1. Algorithmic Ramifications of Prefetching in Memory Hierarchy

      • Akshat Verma, Sandeep Sen
      Pages 9-21

    2. A Cache-Partitioning Aware Replacement Policy for Chip Multiprocessors

      • Haakon Dybdahl, Per Stenström, Lasse Natvig
      Pages 22-34

  5. Session I – Scheduling and Load Balancing

    1. A Security-Oriented Task Scheduler for Heterogeneous Distributed Systems

      • Tao Xie, Xiao Qin
      Pages 35-46

    2. Minimizing Average Response Time for Scheduling Stochastic Workload in Heterogeneous Computational Grids

      • Jie Hu, Raymond Klefstad
      Pages 47-59

    3. Advanced Reservation-Based Scheduling of Task Graphs on Clusters

      • Anthony Sulistio, Wolfram Schiffmann, Rajkumar Buyya
      Pages 60-71

    4. Estimation Based Load Balancing Algorithm for Data-Intensive Heterogeneous Grid Environments

      • Ruchir Shah, Bharadwaj Veeravalli, Manoj Misra
      Pages 72-83

    5. Improving the Flexibility of the Deficit Table Scheduler

      • Raúl Martínez, Francisco J. Alfaro, José L. Sánchez
      Pages 84-97

  6. Session II – Architectures

    1. A Cache-Pinning Strategy for Improving Generational Garbage Collection

      • Vimal K. Reddy, Richard K. Sawyer, Edward F. Gehringer
      Pages 98-110

    2. A Realizable Distributed Ion-Trap Quantum Computer

      • Darshan D. Thaker, Tzvetan S. Metodi, Frederic T. Chong
      Pages 111-122

    3. Segmented Bitline Cache: Exploiting Non-uniform Memory Access Patterns

      • Ravishankar Rao, Justin Wenck, Diana Franklin, Rajeevan Amirtharajah, Venkatesh Akella
      Pages 123-134

    4. Trade-Offs in Transient Fault Recovery Schemes for Redundant Multithreaded Processors

      • Joseph Sharkey, Nayef Abu-Ghazeleh, Dmitry Ponomarev, Kanad Ghose, Aneesh Aggarwal
      Pages 135-147

    5. Supporting Speculative Multithreading on Simultaneous Multithreaded Processors

      • Venkatesan Packirisamy, Shengyue Wang, Antonia Zhai, Wei-Chung Hsu, Pen-Chung Yew
      Pages 148-158
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Editors and Affiliations

  •  ,  

    Yves Robert

  • Department of Electrical and Computer Engineering, Rutgers, the State University of New Jersey, Piscataway, USA

    Manish Parashar

  • Hewlett-Packard ISO, Sy 192, Bangalore, India

    Ramamurthy Badrinath

  • Department of Electrical Engineering, University of Southern California, Los Angeles, USA

    Viktor K. Prasanna

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