Ecole d’Ingénieurs du Canton de Vaud Microelectronics and Systems Institute, Digital Communications Team, Swiss University of Applied Science, Yverdon, Switzerland
Instituto de Microelectrónica de Sevilla-CNM-CSIC Departamento do Diseño Digital Departamento de Electrónica y Electromagnetismo Departamento de Tecnología Electrónica, Universidad de Sevilla
Instituto de Microelectrónica de Sevilla-CNM-CSIC Departamento do Diseño Digital Departamento de Electrónica y Electromagnetismo Departamento de Tecnología Electrónica, Universidad de Sevilla
The International Workshop on Power and Timing Modeling, Optimization, and Simulation PATMOS 2002, was the 12th in a series of international workshops 1 previously held in several places in Europe. PATMOS has over the years evolved into a well-established and outstanding series of open European events on power and timing aspects of integrated circuit design. The increased interest, espe- ally in low-power design, has added further momentum to the interest in this workshop. Despite its growth, the workshop can still be considered as a very - cused conference, featuring high-level scienti?c presentations together with open discussions in a free and easy environment. This year, the workshop has been opened to both regular papers and poster presentations. The increasing number of worldwide high-quality submissions is a measure of the global interest of the international scienti?c community in the topics covered by PATMOS. The objective of this workshop is to provide a forum to discuss and inves- gate the emerging problems in the design methodologies and CAD-tools for the new generation of IC technologies. A major emphasis of the technical program is on speed and low-power aspects with particular regard to modeling, char- terization, design, and architectures. The technical program of PATMOS 2002 included nine sessions dedicated to most important and current topics on power and timing modeling, optimization, and simulation. The three invited talks try to give a global overview of the issues in low-power and/or high-performance circuit design.
Editors and Affiliations
Ecole d’Ingénieurs du Canton de Vaud Microelectronics and Systems Institute, Digital Communications Team, Swiss University of Applied Science, Yverdon, Switzerland
Bertrand Hochet
Instituto de Microelectrónica de Sevilla-CNM-CSIC Departamento do Diseño Digital Departamento de Electrónica y Electromagnetismo Departamento de Tecnología Electrónica, Universidad de Sevilla
Antonio J. Acosta,
Manuel J. Bellido
Bibliographic Information
Book Title: Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Book Subtitle: 12th International Workshop, PATMOS 2002, Seville, Spain, September 11 - 13, 2002
Editors: Bertrand Hochet, Antonio J. Acosta, Manuel J. Bellido
