Reconfigurable Computing: Architectures and Applications

1. Front Matter

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2. Applications

   1. Implementation of Realtime and Highspeed Phase Detector on FPGA

      • Andre Guntoro, Peter Zipf, Oliver Soffke, Harald Klingbeil, Martin Kumm, Manfred Glesner

      Pages 1-11

   2. Case Study: Implementation of a Virtual Instrument on a Dynamically Reconfigurable Platform

      • Gerd Van den Branden, Geert Braeckman, Abdellah Touhafi, Erik Dirkx

      Pages 12-17

   3. Configurable Embedded Core for Controlling Electro-Mechanical Systems

      • Rodrigo Piedade, Leonel Sousa

      Pages 18-23

   4. Evaluation of a Locomotion Algorithm for Worm-Like Robots on FPGA-Embedded Processors

      • J. Gonzalez-Gomez, I. Gonzalez, F. Gomez-Arribas, E. Boemo

      Pages 24-29

   5. Dynamic Partial Reconfigurable FIR Filter Design

      • Yeong-Jae Oh, Hanho Lee, Chong-Ho Lee

      Pages 30-35

   6. Event-Driven Simulation Engine for Spiking Neural Networks on a Chip

      • Rodrigo Agis, Javier Díaz, Eduardo Ros, Richard Carrillo, Eva. M. Ortigosa

      Pages 36-45

   7. Towards an Optimal Implementation of MLP in FPGA

      • E. M. Ortigosa, A. Cañas, R. Rodríguez, J. Díaz, S. Mota

      Pages 46-51

3. Power

   1. Energy Consumption for Transport of Control Information on a Segmented Software-Controlled Communication Architecture

      • Kris Heyrman, Antonis Papanikolaou, Francky Catthoor, Peter Veelaert, Koen Debosschere, Wilfried Philips

      Pages 52-58

   2. Quality Driven Dynamic Low Power Reconfiguration of Handhelds

      • Hiren Joshi, S. S. Verma, G. K. Sharma

      Pages 59-64

   3. An Efficient Estimation Method of Dynamic Power Dissipation on VLSI Interconnects

      • Joong-ho Park, Bang-Hyun Sung, Seok-Yoon Kim

      Pages 65-74

4. Image Processing

   1. Highly Paralellized Architecture for Image Motion Estimation

      • Javier Díaz, Eduardo Ros, Sonia Mota, Rafael Rodriguez-Gomez

      Pages 75-86

   2. Design Exploration of a Video Pre-processor for an FPGA Based SoC

      • Niklas Lepistö, Benny Thörnberg, Mattias O’Nils

      Pages 87-92

   3. QUKU: A Fast Run Time Reconfigurable Platform for Image Edge Detection

      • Sunil Shukla, Neil W. Bergmann, Jürgen Becker

      Pages 93-98

   4. Applications of Small-Scale Reconfigurability to Graphics Processors

      • Kevin Dale, Jeremy W. Sheaffer, Vinu Vijay Kumar, David P. Luebke, Greg Humphreys, Kevin Skadron

      Pages 99-108

   5. An Embedded Multi-camera System for Simultaneous Localization and Mapping

      • Vanderlei Bonato, José A. de Holanda, Eduardo Marques

      Pages 109-114

   6. Performance/Cost Trade-Off Evaluation for the DCT Implementation on the Dynamically Reconfigurable Processor

      • Vu Manh Tuan, Yohei Hasegawa, Naohiro Katsura, Hideharu Amano

      Pages 115-121

   7. Trigonometric Computing Embedded in a Dynamically Reconfigurable CORDIC System-on-Chip

      • Francisco Fons, Mariano Fons, Enrique Cantó, Mariano López

      Pages 122-127

   8. Handel-C Design Enhancement for FPGA-Based DV Decoder

      • Sławomir Cichoń, Marek Gorgoń, Mirosław Pac

      Pages 128-133

   9. Run-Time Resources Management on Coarse Grained, Packet-Switching Reconfigurable Architecture: A Case Study Through the APACHES’ Platform

      • Alex Ngouanga, Gilles Sassatelli, Lionel Torres, Thierry Gil, André Borin Suarez, Altamiro Amadeu Susin

      Pages 134-145

1 The International Workshop on Recon?gurable Computing (ARC) started in 2005 in Algarve, Portugal. The major motivation was to create an event where on-going research e?orts as well as more elaborated, interesting and hi- quality work on applied recon?gurable computing could be presented and d- cussed. Over the last couple of years recon?gurable computing has become a we- known and established research area producing interesting as well as important results in both general and embedded computing systems. It is also getting more and more interest from industry which is attracted by the (design and development) ?exibility as well as the performance improvements that can be expected from this technology. As recon?gurablecomputing has blurred the gap between software and hardware, some even speak of a radical new programming paradigm opening a new realm of unseen applications and opportunities. The logo of the ARC workshop is the Nonius, a measurement instrument used in the Portuguese period of discoveries that was invented by Pedro Nunes, a Portuguesemathematician. As the logo suggests,the main motto of ARC is to help to navigate the world of recon?gurable computing. Driven by this motto, we hope ARC contributes to solid advances on recon?gurable computing.

• EPIC
• Hardwarebeschreibungssprache
• QoS
• Scheduling
• computer architecture
• computer networking
• configuration
• energy efficiency
• image processing
• network on chip (NoC)
• neutral networks
• optimization
• organization
• performance analysis
• system on chip (SoC)

• TU Delft, Computer Engineering Laboratory, EEMCS, The Netherlands

  Koen Bertels

• IST/INESC-ID, Lisboa, Portugal

  João M. P. Cardoso

• TUDelft., Computer Engineering Lab, Delft, The Netherlands

  Stamatis Vassiliadis

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