Variation Tolerant On-Chip Interconnects

1. Front Matter

   Pages i-xi

   PDF

2. Introduction

   • Ethiopia Enideg Nigussie

   Pages 1-10

3. Interconnect Design Techniques

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   Pages 11-23

4. On-Chip Wire Modeling

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   Pages 25-34

5. Design of Delay-Insensitive Current Sensing Interconnects

   • Ethiopia Enideg Nigussie

   Pages 35-69

6. Enhancing Completion Detection Performance

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   Pages 71-91

7. Energy Efficient Semi-Serial Interconnect

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   Pages 93-117

8. Comparison of the Designed Interconnects

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   Pages 119-125

9. Circuit Techniques for PVT Variation Tolerance

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   Pages 127-156

10. Back Matter

    Pages 157-170

    PDF

This book presents design techniques, analysis and implementation of high performance and power efficient, variation tolerant on-chip interconnects. Given the design paradigm shift to multi-core, interconnect-centric designs and the increase in sources of variability and their impact in sub-100nm technologies, this book will be an invaluable reference for anyone concerned with the design of next generation, high-performance electronics systems.

• Analog Circuits and Signal Processing
• Energy efficient interconnect
• Interconnection networks
• Low Power Design
• Network on Chip
• On-chip communication
• On-chip interconnect
• Power Management
• Variation tolerant interconnect

• University of Turku, Turku, Finland

  Ethiopia Enideg Nigussie

Introduction.- Interconnect Design Techniques.- On-Chip Wire Modeling.- Design of Delay-Insensitive Current Sensing Interconnects.- Enhancing Completion Detection Performance.- Energy Efficient Semi-Serial Interconnect.- Comparison of the Designed Interconnects.- Circuit Techniques for PVT Variation Tolerance.

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