Skip to main content
SpringerLink
Log in
SpringerLink
Log in

VLSI for Neural Networks and Artificial Intelligence

  • Book
  • © 1994

Overview

Editors:
  1. José G. Delgado-Frias

    1. State University of New York at Binghamton, Binghamton, USA

    View editor publications

    You can also search for this editor in PubMed   Google Scholar

  2. William R. Moore

    1. Oxford University, Oxford, UK

    View editor publications

    You can also search for this editor in PubMed   Google Scholar

This is a preview of subscription content, log in via an institution to check access.

Access this book

Log in via an institution
eBook USD 129.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Other ways to access

Licence this eBook for your library

Institutional subscriptions

Table of contents (30 chapters)

  1. Front Matter

    Pages i-x
    Download chapter PDF

  2. Analog Circuits for Neural Networks

    1. Analog VLSI Neural Learning Circuits — A Tutorial

      • Howard C. Card
      Pages 1-23

    2. An Analog CMOS Implementation of a Kohonen Network with Learning Capability

      • Oliver Landolt
      Pages 25-34

    3. Back-Propagation Learning Algorithms for Analog VLSI Implementation

      • Maurizio Valle, Daniele D. Caviglia, Giacomo M. Bisio
      Pages 35-44

    4. An Analog Implementation of the Boltzmann Machine with Programmable Learning Algorithms

      • V. Lafargue, P. Garda, E. Belhaire
      Pages 45-52

    5. A VLSI Design of the Minimum Entropy Neuron

      • Rüdiger W. Brause
      Pages 53-60

    6. A Multi-Layer Analog VLSI Architecture for Texture Analysis Isomorphic to Cortical Cells in Mammalian Visual System

      • Luigi Raffo, Giacomo M. Bisio, Daniele D. Caviglia, Giacomo Indiveri, Silvio P. Sabatini
      Pages 61-70

  3. Digital Implementations of Neural Networks

    1. A VLSI Pipelined Neuroemulator

      • José G. Delgado-Frias, Stamatis Vassiliadis, Gerald G. Pechanek, Wei Lin, Steven M. Barber, Hui Ding
      Pages 71-80

    2. A Low Latency Digital Neural Network Architecture

      • William Fornaciari, Fabio Salice
      Pages 81-91

    3. MANTRA: A Multi-Model Neural-Network Computer

      • Marc A. Viredaz, Christian Lehmann, François Blayo, Paolo Ienne
      Pages 93-102

    4. SPERT: A Neuro-Microprocessor

      • Krste Asanović, James Beck, Brian E. D. Kingsbury, Phil Kohn, Nelson Morgan, John Wawrzynek
      Pages 103-107

    5. Design of Neural Self-Organization Chips for Semantic Applications

      • Tadashi Ae, Reiji Aibara, Kazumasa Kioi
      Pages 109-117

    6. VLSI Implementation of a Digital Neural Network with Reward-Penalty Learning

      • Terence Hui, Paul Morgan, Hamid Bolouri, Kevin Gurney
      Pages 119-127

    7. Asynchronous VLSI Design for Neural System Implementation

      • John F. Hurdle, Erik L. Brunvand, Lüli Josephson
      Pages 129-139

  4. Neural Networks on Multiprocessor Systems and Applications

    1. VLSI-Implementation of Associative Memory Systems for Neural Information Processing

      • Andreas König, Manfred Glesner
      Pages 141-150

    2. A Dataflow Approach for Neural Networks

      • Thomas F. Ryan, José G. Delgado-Frias, Stamatis Vassiliadis, Gerald G. Pechanek, Douglas M. Green
      Pages 151-158

    3. A Custom Associative Chip Used as a Building Block for a Software Reconfigurable Multi-Network Simulator

      • Jean-Dominique Gascuel, Eric Delaunay, Lionel Montoliu, Bahram Moobed, Michel Weinfeld
      Pages 159-166

    4. Parallel Implementation of Neural Associative Memories on RISC Processors

      • U. Rückert, S. Rüping, E. Naroska
      Pages 167-176

    5. Reconfigurable Logic Implementation of Memory-Based Neural Networks: A Case Study of the CMAC Network

      • Aleksander R. Kolcz, Nigel M. Allinson
      Pages 177-186

    6. A Cascadable VLSI Design for GENET

      • Chang J. Wang, Edward P. K. Tsang
      Pages 187-196
Back to top

Keywords

About this book

Neural network and artificial intelligence algorithrns and computing have increased not only in complexity but also in the number of applications. This in turn has posed a tremendous need for a larger computational power that conventional scalar processors may not be able to deliver efficiently. These processors are oriented towards numeric and data manipulations. Due to the neurocomputing requirements (such as non-programming and learning) and the artificial intelligence requirements (such as symbolic manipulation and knowledge representation) a different set of constraints and demands are imposed on the computer architectures/organizations for these applications. Research and development of new computer architectures and VLSI circuits for neural networks and artificial intelligence have been increased in order to meet the new performance requirements. This book presents novel approaches and trends on VLSI implementations of machines for these applications. Papers have been drawn from a number of research communities; the subjects span analog and digital VLSI design, computer design, computer architectures, neurocomputing and artificial intelligence techniques. This book has been organized into four subject areas that cover the two major categories of this book; the areas are: analog circuits for neural networks, digital implementations of neural networks, neural networks on multiprocessor systems and applications, and VLSI machines for artificial intelligence. The topics that are covered in each area are briefly introduced below.

Editors and Affiliations

  • State University of New York at Binghamton, Binghamton, USA

    José G. Delgado-Frias

  • Oxford University, Oxford, UK

    William R. Moore

Bibliographic Information

Publish with us

Policies and ethics

Back to top

Search

Navigation