Editors:
- Provides a comprehensive overview of routing algorithms for Networks-on-Chip and NoC-based, manycore systems
- Describes routing algorithms for NoC architectures at all abstraction levels, from the algorithmic level to actual implementation
- Discusses the impact on NoC routing algorithms of key design objectives, such as power dissipation, energy consumption, thermal aspects, reliability, and performance
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Table of contents (14 chapters)
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Front Matter
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Multicast Communication
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Front Matter
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Fault Tolerance and Reliability
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Front Matter
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Power/Energy and Thermal Issues
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Front Matter
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Industrial Case Study
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Front Matter
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About this book
Keywords
- Adaptive Routing in Network on Chip
- Network on Chip
- Network on Chip Routing Architecture
- On-Chip Communication Architecture
- Routing Algorithms for Intel 80-Core Chip
- Routing Algorithms for Manycore Chips
- Routing Algorithms for NXP Athereal
- Routing Algorithms for Network on Chip
- Routing Algorithms for ST Spidergon
- Routing Algorithms for TILERA 100-Core Chip
Editors and Affiliations
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Facoltà di Ingegneria, Università degli Studi di Enna, 'Kore', Enna, Italy
Maurizio Palesi
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Department of IT, University of Turku, Turku, Finland
Masoud Daneshtalab
Bibliographic Information
Book Title: Routing Algorithms in Networks-on-Chip
Editors: Maurizio Palesi, Masoud Daneshtalab
DOI: https://doi.org/10.1007/978-1-4614-8274-1
Publisher: Springer New York, NY
eBook Packages: Engineering, Engineering (R0)
Copyright Information: Springer Science+Business Media New York 2014
Hardcover ISBN: 978-1-4614-8273-4
Softcover ISBN: 978-1-4939-5511-4
eBook ISBN: 978-1-4614-8274-1
Edition Number: 1
Number of Pages: XIV, 410
Number of Illustrations: 122 b/w illustrations, 97 illustrations in colour
Topics: Circuits and Systems, Processor Architectures, Electronics and Microelectronics, Instrumentation