VHDL for Simulation, Synthesis and Formal Proofs of Hardware

1. Front Matter

   Pages i-ix

   PDF

2. Introduction

   1. Evolutionary Processes in Language, Software, and System Design

      • F. Erich Marschner

      Pages 1-13

3. Simulation

   1. Front Matter

      Pages 15-15

      PDF

   2. Timing Constraint Checks in VHDL—a comparative study

      • Fuhong Liu, Adam Pawlak

      Pages 17-32

   3. Using Formalized Timing Diagrams in VHDL Simulation

      • M. Dufresne, K. Khordoc, E. Cerny

      Pages 33-42

   4. Switch-Level Models in Multi-level VHDL Simulations

      • K. Khordoc, M. Biotteau, E. Cerny

      Pages 43-62

   5. Bi-directional Switches in VHDL using the 46 Value System

      • Alec Stanculescu

      Pages 63-71

   6. Systems Real Time Analysis with VHDL Generated from Graphical SA-VHDL

      • Matti Sipola, Juha-Pekka Soininen, Jorma Kivelä

      Pages 73-86

   7. Delay Calculation and Back Annotation in VHDL Addressing the Requirements of ASIC Design

      • Peter Connor, Sanjay Nayak, Joyce Kraley, Victor Berman

      Pages 87-98

4. Synthesis

   1. Front Matter

      Pages 99-99

      PDF

   2. A VHDL-Driven Synthesis Environment

      • Haluk Konuk, F. Erich Marschner

      Pages 101-115

   3. VHDL Specific Issues in High Level Synthesis

      • Adam Postula

      Pages 117-133

   4. ASIC Design Using Silicon 1076

      • Robert A. Cottrell

      Pages 135-147

   5. Generating VHDL for Simulation and Synthesis from a High-Level DSP Design Tool

      • Lars Lundberg

      Pages 149-161

   6. Aspects of Optimization and Accuracy for VHDL Synthesis

      • John Elliott, Paul Harper

      Pages 163-175

5. Formal Verifications and Semantics

   1. Front Matter

      Pages 177-177

      PDF

   2. Symbolic Computation of Hierarchical and Interconnected FSMS

      • Alain Debreil, Christian Berthet, Ahmed Jerraya

      Pages 179-193

   3. Formal semantics of VHDL timing constructs

      • Ashraf Salem, Dominique Borrione

      Pages 195-206

   4. A Structural Information Model of VHDL

      • R. A. J. Marshall, H. J. Kahn

      Pages 207-225

   5. Formal verification of VHDL descriptions in Boyer-Moore : first results

      • Dominique Borrione, Laurence Pierre, Ashraf Salem

      Pages 227-243

The success of VHDL since it has been balloted in 1987 as an IEEE standard may look incomprehensible to the large population of hardware designers, who had never heared of Hardware Description Languages before (for at least 90% of them), as well as to the few hundreds of specialists who had been working on these languages for a long time (25 years for some of them). Until 1988, only a very small subset of designers, in a few large companies, were used to describe their designs using a proprietary HDL, or sometimes a HDL inherited from a University when some software environment happened to be developped around it, allowing usability by third parties. A number of benefits were definitely recognized to this practice, such as functional verification of a specification through simulation, first performance evaluation of a tentative design, and sometimes automatic microprogram generation or even automatic high level synthesis. As there was apparently no market for HDL's, the ECAD vendors did not care about them, start-up companies were seldom able to survive in this area, and large users of proprietary tools were spending more and more people and money just to maintain their internal system.

• ASIC
• C programming language
• Constraint
• VHDL
• circuit design
• computer-aided design (CAD)
• formal verification
• model
• modeling
• simulation
• verification

• Institut Méditerranéen de Technologie, Germany

  Jean Mermet

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