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The Interaction of Compilation Technology and Computer Architecture

  • Book
  • © 1994

Overview

Editors:
  1. David J. Lilja

    1. University of Minnesota, Minneapolis, USA

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    You can also search for this editor in PubMed   Google Scholar

  2. Peter L. Bird

    1. Advanced Computer Research Institute, Lyon, France

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Table of contents (10 chapters)

  1. Front Matter

    Pages i-viii
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  2. Introduction and Overview

    • David J. Lilja, Peter L. Bird, Richard Y. Kain
    Pages 1-12

  3. Architectural Support for Compile-Time Speculation

    • Michael D. Smith
    Pages 13-49

  4. Register Requirements for High Performance Code Scheduling

    • Bill Mangione-Smith
    Pages 51-86

  5. Data Dependencies in Decoupled, Pipelined Loops

    • Peter L. Bird
    Pages 87-118

  6. The Effects of Traditional Compiler Optimizations on Superscalar Architectural Design

    • Thomas M. Conte, Kishore N. P. Menezes
    Pages 119-136

  7. Dynamic Program Monitoring and Transformation using the OMOS Object Server

    • Douglas B. Orr, Robert W. Mecklenburg, Peter J. Hoogenboom, Jay Lepreau
    Pages 137-159

  8. Performance Limits of Compiler-Directed Multiprocessor Cache Coherence Enforcement

    • Farnaz Mounes-Toussi, David J. Lilja
    Pages 161-190

  9. Compiling HPF for Distributed Memory MIMD Computers

    • Zeki Bozkus, Alok Choudhary, Tomasz Haupt, Geoffrey Fox, Sanjay Ranka
    Pages 191-221

  10. The Influence of the Object-Oriented Language Model on a Supporting Architecture

    • Mario Wolczko, Ifor Williams
    Pages 223-247

  11. Project Triton: Towards Improved Programmability of Parallel Computers

    • Michael Philippsen, Thomas M. Warschko, Walter F. Tichy, Christian G. Herter, Ernst A. Heinz, Paul Lukowicz
    Pages 249-281

  12. Back Matter

    Pages 283-285
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Keywords

About this book

In brief summary, the following results were presented in this work: • A linear time approach was developed to find register requirements for any specified CS schedule or filled MRT. • An algorithm was developed for finding register requirements for any kernel that has a dependence graph that is acyclic and has no data reuse on machines with depth independent instruction templates. • We presented an efficient method of estimating register requirements as a function of pipeline depth. • We developed a technique for efficiently finding bounds on register require­ ments as a function of pipeline depth. • Presented experimental data to verify these new techniques. • discussed some interesting design points for register file size on a number of different architectures. REFERENCES [1] Robert P. Colwell, Robert P. Nix, John J O'Donnell, David B Papworth, and Paul K. Rodman. A VLIW Architecture for a Trace Scheduling Com­ piler. In Architectural Support for Programming Languages and Operating Systems, pages 180-192, 1982. [2] C. Eisenbeis, W. Jalby, and A. Lichnewsky. Compile-Time Optimization of Memory and Register Usage on the Cray-2. In Proceedings of the Second Workshop on Languages and Compilers, Urbana l/inois, August 1989. [3] C. Eisenbeis, William Jalby, and Alain Lichnewsky. Squeezing More CPU Performance Out of a Cray-2 by Vector Block Scheduling. In Proceedings of Supercomputing '88, pages 237-246, 1988. [4] Michael J. Flynn. Very High-Speed Computing Systems. Proceedings of the IEEE, 54:1901-1909, December 1966.

Editors and Affiliations

  • University of Minnesota, Minneapolis, USA

    David J. Lilja

  • Advanced Computer Research Institute, Lyon, France

    Peter L. Bird

Bibliographic Information

  • Book Title: The Interaction of Compilation Technology and Computer Architecture

  • Editors: David J. Lilja, Peter L. Bird

  • DOI: https://doi.org/10.1007/978-1-4615-2684-1

  • Publisher: Springer New York, NY

  • eBook Packages: Springer Book Archive

  • Copyright Information: Springer Science+Business Media New York 1994

  • Hardcover ISBN: 978-0-7923-9451-8Published: 31 May 1994

  • Softcover ISBN: 978-1-4613-6154-1Published: 04 October 2012

  • eBook ISBN: 978-1-4615-2684-1Published: 06 December 2012

  • Edition Number: 1

  • Number of Pages: VIII, 285

  • Topics: Processor Architectures, Programming Languages, Compilers, Interpreters, Operating Systems

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