Skip to main content
  • Book
  • © 1990

Testing and Reliable Design of CMOS Circuits

Buy it now

Buying options

eBook USD 129.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Other ways to access

This is a preview of subscription content, log in via an institution to check for access.

Table of contents (7 chapters)

  1. Front Matter

    Pages i-xiii
  2. Introduction

    • Niraj K. Jha, Sandip Kundu
    Pages 1-30
  3. Test Invalidation

    • Niraj K. Jha, Sandip Kundu
    Pages 31-42
  4. Test Generation for Dynamic CMOS Circuits

    • Niraj K. Jha, Sandip Kundu
    Pages 43-85
  5. Test Generation for Static CMOS Circuits

    • Niraj K. Jha, Sandip Kundu
    Pages 87-130
  6. Design for Robust Testability

    • Niraj K. Jha, Sandip Kundu
    Pages 131-175
  7. Self-Checking Circuits

    • Niraj K. Jha, Sandip Kundu
    Pages 177-221
  8. Conclusions

    • Niraj K. Jha, Sandip Kundu
    Pages 223-225
  9. Back Matter

    Pages 227-231

About this book

In the last few years CMOS technology has become increas­ ingly dominant for realizing Very Large Scale Integrated (VLSI) circuits. The popularity of this technology is due to its high den­ sity and low power requirement. The ability to realize very com­ plex circuits on a single chip has brought about a revolution in the world of electronics and computers. However, the rapid advance­ ments in this area pose many new problems in the area of testing. Testing has become a very time-consuming process. In order to ease the burden of testing, many schemes for designing the circuit for improved testability have been presented. These design for testability techniques have begun to catch the attention of chip manufacturers. The trend is towards placing increased emphasis on these techniques. Another byproduct of the increase in the complexity of chips is their higher susceptibility to faults. In order to take care of this problem, we need to build fault-tolerant systems. The area of fault-tolerant computing has steadily gained in importance. Today many universities offer courses in the areas of digital system testing and fault-tolerant computing. Due to the impor­ tance of CMOS technology, a significant portion of these courses may be devoted to CMOS testing. This book has been written as a reference text for such courses offered at the senior or graduate level. Familiarity with logic design and switching theory is assumed. The book should also prove to be useful to professionals working in the semiconductor industry.

Authors and Affiliations

  • Princeton University, USA

    Niraj K. Jha

  • T.J. Watson Research Center, IBM, USA

    Sandip Kundu

Bibliographic Information

Buy it now

Buying options

eBook USD 129.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Other ways to access