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System-on-Chip Methodologies & Design Languages

  • Book
  • © 2001

Overview

Editors:
  1. Peter J. Ashenden

    1. Ashenden Designs Pty. Ltd., Australia

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    You can also search for this editor in PubMed   Google Scholar

  2. Jean P. Mermet

    1. ECSI, France

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  3. Ralf Seepold

    1. Universität Karlsruhe, Germany

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Table of contents (28 chapters)

  1. Front Matter

    Pages i-x
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  2. VHDL Trends

    1. Front Matter

      Pages 1-1
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    2. VHDL in 2005 — The Requirements

      • Robert H. Klenke, James H. Aylor, Paul Menchini, Ron Waxman, William Anderson, Jack Stinson
      Pages 3-12

    3. Application of VHDL Features for Optimisation of Functional Validation Quality Measurement

      • Celia López, Teresa Riesgo, Yago Torroja, Javier Uceda, Luis Entrena
      Pages 13-24

    4. An Object-Oriented Component Model Using Standard VHDL for Mixed Abstraction Level Design

      • C. Hansen, O. Bringmann, W. Rosenstiel
      Pages 25-36

    5. A VHDL-Centric Mixed-Language Simulation Environment

      • A. Windisch, D. Monjau, T. Schneider, J. Mades, M. Glesner, W. Ecker
      Pages 37-46

    6. Analogue circuit synthesis from VHDL-AMS

      • Tom J. Kazmierski, Fazrena A. Hamid
      Pages 47-56

  3. Formal Verification

    1. Front Matter

      Pages 57-57
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    2. Symbolic Simulation and Verification of VHDL with ACL2

      • Dominique Borrione, Philippe Georgelin, Vanderlei Moraes Rodrigues
      Pages 59-69

    3. Functional Verification with Embedded Checkers

      • Scott Switzer, David Landoll, Thomas Anderson
      Pages 71-80

    4. Improved Design Verification by Random Simulation Guided by Genetic Algorithms

      • Pierre Faye, Eduard Cerny
      Pages 81-95

    5. VERIS: An Efficient Model Checker for Synchronous VHDL Designs

      • Yiping Fan, Jinsong Bei, Jinian Bian, Hongxi Xue, Xianlong Hong, Jun Gu
      Pages 97-107

  4. Synthesis

    1. Front Matter

      Pages 109-109
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    2. Title On Flip-flop Inference in HDL Synthesis

      • Hen-Ming Lin, Jing-Yang Jou
      Pages 111-122

    3. Synthesis Oriented Communication Design for Structural Hardware Objects

      • Wolfram Putzke-Röming, Wolfgang Nebel
      Pages 123-134

    4. High-Level Synthesis through Transforming VHDL Models

      • Anatoly Prihozhy
      Pages 135-146

  5. Specification Formalisms

    1. Front Matter

      Pages 147-147
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    2. Multi-Facetted Modeling

      • Perry Alexander, David Barton
      Pages 149-159

    3. A Dual Spring System Case-Study Model in Rosetta

      • Peter J. Ashenden, Perry Alexander, David L. Barton
      Pages 161-170

    4. Transformational System Design Based on Formal Computational Model and Skeletons

      • Wenbiao Wu, Ingo Sander, Axel Jantsch
      Pages 171-185
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Keywords

About this book

System-on-Chip Methodologies & Design Languages brings together a selection of the best papers from three international electronic design language conferences in 2000. The conferences are the Hardware Description Language Conference and Exhibition (HDLCon), held in the Silicon Valley area of USA; the Forum on Design Languages (FDL), held in Europe; and the Asia Pacific Chip Design Language (APChDL) Conference. The papers cover a range of topics, including design methods, specification and modeling languages, tool issues, formal verification, simulation and synthesis. The results presented in these papers will help researchers and practicing engineers keep abreast of developments in this rapidly evolving field.

Editors and Affiliations

  • Ashenden Designs Pty. Ltd., Australia

    Peter J. Ashenden

  • ECSI, France

    Jean P. Mermet

  • Universität Karlsruhe, Germany

    Ralf Seepold

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