Overview
- Is intended for design engineers and researchers in the field of VLSI and embedded system design
- Introduces readers to deterministic and simulation-based algorithms for testing crosstalk delay faults in VLSI circuits
- Provides a review of various test generation algorithms for crosstalk delay faults
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Table of contents (10 chapters)
Keywords
About this book
Authors and Affiliations
About the authors
Dr. M.C. Bhuvaneswari is an Associate Professor at the Department of Electrical and Electronics Engineering, PSG College of Technology, Coimbatore, India. She received her BE in Electronics and Communications Engineering from Madras University, and her ME and PhD from Bharathiar University. Her research interests include Applied Electronics, VLSI Design and Testing, Genetic Algorithms, Digital System Design, and Microprocessors. She has published a book on VLSI and Embedded systems (2015) and authored more than 90 research papers in journals and for national and international conferences. She is a life member of Indian Society for Technical Education, Institute of Engineers (India), Computer Society of India and Systems Society of India. Prof Bhuvaneswari was honored with Dakshinamoorthy award instituted by PSG College of Technology for Teaching Excellence in the year 2010
Bibliographic Information
Book Title: Test Generation of Crosstalk Delay Faults in VLSI Circuits
Authors: S. Jayanthy, M.C. Bhuvaneswari
DOI: https://doi.org/10.1007/978-981-13-2493-2
Publisher: Springer Singapore
eBook Packages: Engineering, Engineering (R0)
Copyright Information: Springer Science+Business Media Singapore 2019
Hardcover ISBN: 978-981-13-2492-5Published: 10 October 2018
Softcover ISBN: 978-981-13-4784-9Published: 21 December 2018
eBook ISBN: 978-981-13-2493-2Published: 20 September 2018
Edition Number: 1
Number of Pages: XI, 156
Number of Illustrations: 42 b/w illustrations, 7 illustrations in colour
Topics: Circuits and Systems, Control Structures and Microprogramming, Performance and Reliability, Logic Design