Computer Engineering and Technology

1. Front Matter

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2. Processor Architecture

   1. An Efficient Vector Memory Unit for SIMD DSP

      • Haiyan Chen, Zhong Liu, Sheng Liu, Sheng Ma

      Pages 1-11

   2. An Analytical Model for Matrix Multiplication on Many Threaded Vector Processors

      • Yongwen Wang, Jun Gao, Bingcai Sui, Chengyi Zhang, Weixia Xu

      Pages 12-19

   3. HMCPA: Heuristic Method Utilizing Critical Path Analysis for Design Space Exploration of Superscalar Microprocessors

      • Fangyan Qin, Lei Wang, Yu Deng, Yongwen Wang, Tianlei Zhao

      Pages 20-35

   4. Low Latency Multicasting Scheme for Bufferless Hybrid NoC-Bus 3D On-Chip Networks

      • Chaoyun Yao, Chaochao Feng, Mingxuan Zhang, Shaojun Wei

      Pages 36-47

   5. A Highly-Efficient Crossbar Allocator Architecture for High-Radix Switch

      • Mingche Lai, Lei Gao

      Pages 48-58

3. Application Specific Processors

   1. FPGA Implementation of FastICA Algorithm for On-line EEG Signal Separation

      • Dongsheng Zhao, Jiang Jiang, Chang Wang, Baoliang Lu, Yongxin Zhu

      Pages 59-68

   2. FPGA Based Low-Latency Market Data Feed Handler

      • Liyuan Zhou, Jiang Jiang, Ruochen Liao, Tianyi Yang, Chang Wang

      Pages 69-77

   3. FPGA-Based Real-Time Emulation for High-Speed Double-Precision Small Time-Step Electromagnetic Transient System

      • Jianxing Li, Chunhui Ding, Guanghui He, Qing Mu

      Pages 78-88

   4. Nodal-Analysis-Based FPGA Implementation for Real-Time Electromagnetic Transient Emulation System

      • Xiaozhang Gong, Tianyi Yang, Xing Zhang, Guanghui He

      Pages 89-98

   5. Low Complexity Algorithm and VLSI Design of Joint Demosaicing and Denoising for Digital Still Camera

      • Liang Hong, Wei Jin, Guanghui He, Weifeng He, Zhigang Mao

      Pages 99-107

4. Computer Application and Software Optimization

   1. A Slide-Window-Based Hardware XML Parsing Accelerator

      • Linan Huang, Jiang Jiang, Chang Wang, Yanghan Wang, Yan Pei

      Pages 108-117

   2. Design of Fully Pipelined Dual-Mode Double Precision Reduction Circuit on FPGAs

      • Song Guo, Yong Dou, Yuanwu Lei

      Pages 118-125

   3. Design of Cloud Server Based on Godson Processors

      • Chaoqun Sha, Gongbo Li, Chenming Zheng, Yanping Gao, Xiaojun Yang, Chungjin Hu

      Pages 126-139

   4. A New Storage System for Exabytes Storage

      • Haitao Chen, Jinwen Li, Wei Zhang

      Pages 140-147

   5. A High-Accuracy Clock Synchronization Method in Distributed Real-Time System

      • Hongliang Li, Xuan Feng, Song Shi, Fang Zheng, Xianghui Xie

      Pages 148-157

   6. Soft-Input Soft-Output Parallel Stack Algorithm for MIMO Detection

      • Fan Luo, Zhiting Yan, Guanghui He, Jun Ma, Zhigang Mao

      Pages 158-169

5. Technology on the Horizon

   1. Current Reduction Phenomenon in Graphene-Based Device

      • Honghui Sun, Liang Fang

      Pages 170-175

   2. Dynamic Mapping Optimization for LSQ Soft Error Rate Reduction under 3D Integration Technology

      • Chao Song, Min-xuan Zhang

      Pages 176-183

6. Back Matter

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This book constitutes the refereed proceedings of the 18th National Conference on Computer Engineering and Technology, NCCET 2014, held in Guiyang, China, during July/August 2014. The 18 papers presented were carefully reviewed and selected from 85 submissions. They are organized in topical sections on processor architecture; computer application and software optimization; technology on the horizon.

• circuit design
• hardware implementation
• network on chip
• performance modeling and analysis
• processor architecture

• National University of Defense Technology, Changsha, China

  Weixia Xu, Liquan Xiao

• National University of Defense Technology, Changsha, P.R. China

  Jinwen Li, Zhenzhen Zhu

• School of Computer, National University of Defense Technology, Changsha, P.R. China

  Chengyi Zhang

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