Architecture Design and Validation Methods

1. Front Matter

   Pages I-IX

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2. Modeling and Synthesis of Behavior, Control and Data Flow

   • Raul Camposano, Andrew Seawright, Joseph Buck

   Pages 1-48

3. Cell-based Logic Optimization

   • Giovanni De Micheli

   Pages 49-87

4. A Design Flow for Performance Planning: New Paradigms for Iteration Free Synthesis

   • Ralph H. J. M. Otten

   Pages 89-139

5. Test and Testable Design

   • Hans-Joachim Wunderlich

   Pages 141-190

6. Machine Assisted Verification

   • Hans Eveking

   Pages 191-242

7. Models of Computation for System Design

   • Luciano Lavagno, Alberto Sangiovanni-Vincentelli, Ellen M. Sentovich

   Pages 243-295

8. Modular Design for the Java Virtual Machine Architecture

   • Egon Börger, Wolfram Schulte

   Pages 297-357

This book grew out of material which was taught at the International Summer School on Architecture Design and Validation Methods, held June 23-July 5, 1997, on the Island of Lipari and directed to graduate students and young researchers. Since then the course notes have been completely elaborated and extended and additional chapters have been added so that this book offers a comprehensive presentation of the state of the art which leads the reader to the forefront of the current research in the area. The chapters, each of which was written by a group of eminent special­ ists in the field, are self-contained and can be read independently of each other. They cover the wide range of theoretical and practical methods which currently used for the specification, design, validation and verification of are hardware/software architectures. Synthesis methods are the subject of the first three chapters. The chapter on Modeling and Synthesis of Behavior, Control and Data Flow focusses on techniques above the register-transfer level. The chapter on Cell-Based Logic Optimizations concentrates on methods that interface logic design with phys­ ical design, in particular on techniques for cell-library binding, the back-end of logic synthesis. The chapter on A Design Flow for Performance Planning presents new paradigms for iteration-free synthesis where global wire plans for meeting timing constraints already appear at the conceptual design stage, even before fixing the functionality of the blocks in the plan.

• Design of computer architectures
• Design von Rechnerarchitekturen
• Modeling and behav ioral synthesis
• Modellierung und Synthese
• Rechnerarchitektur
• Testability
• Testbarkeit
• Validation of computer architectures
• Validier
• computer
• computer architecture

• Dipartimento di Informatica, Università di Pisa, Pisa, Italy

  Egon Börger

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