VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design

1. Front Matter

   PDF

2. FPGA-Based High-Speed Authenticated Encryption System

   • Michael Muehlberghuber, Christoph Keller, Frank K. Gürkaynak, Norbert Felber

   Pages 1-20

3. A Smart Memory Accelerated Computed Tomography Parallel Backprojection

   • Qiuling Zhu, Larry Pileggi, Franz Franchettis

   Pages 21-44

4. Trinocular Stereo Vision Using a Multi Level Hierarchical Classification Structure

   • Andy Motten, Luc Claesen, Yun Pan

   Pages 45-63

5. Spatially-Varying Image Warping: Evaluations and VLSI Implementations

   • Pierre Greisen, Michael Schaffner, Danny Luu, Val Mikos, Simon Heinzle, Frank K. Gürkaynak et al.

   Pages 64-87

6. An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing

   • Jeremy Constantin, Ahmed Dogan, Oskar Andersson, Pascal Meinerzhagen, Joachim Rodrigues, David Atienza et al.

   Pages 88-106

7. Configurable Low-Latency Interconnect for Multi-core Clusters

   • Giulia Beanato, Igor Loi, Giovanni De Micheli, Yusuf Leblebici, Luca Benini

   Pages 107-124

8. A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks

   • Zhibin Xiao, Bevan Baas

   Pages 125-143

9. Fault-Tolerant Techniques to Manage Yield and Power Constraints in Network-on-Chip Interconnections

   • Anelise Kologeski, Caroline Concatto, Fernanda Lima Kastensmidt, Luigi Carro

   Pages 144-161

10. On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors

    • Davide Sabena, Luca Sterpone, Matteo Sonza Reorda

    Pages 162-180

11. SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture

    • Seokjoong Kim, Matthew R. Guthaus

    Pages 181-195

12. CMOS Implementation of Threshold Gates with Hysteresis

    • Farhad A. Parsan, Scott C. Smith

    Pages 196-216

13. Simulation and Experimental Characterization of a Unified Memory Device with Two Floating-Gates

    • Neil Di Spigna, Daniel Schinke, Srikant Jayanti, Veena Misra, Paul Franzon

    Pages 217-233

14. Back Matter

    PDF

This book contains extended and revised versions of the best papers presented at the 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, held in Santa Cruz, CA, USA, in October 2012. The 12 papers included in the book were carefully reviewed and selected from the 33 full papers presented at the conference. The papers cover a wide range of topics in VLSI technology and advanced research. They address the current trend toward increasing chip integration and technology process advancements bringing about stimulating new challenges both at the physical and system-design levels, as well as in the test of these systems.

• adaptive routing
• multi-core processor
• network-on-chip
• smart memory
• threshold gates

• EPFL, Lausanne, Switzerland

  Andreas Burg

• Boston University, USA

  Ayṣe Coṣkun

• University of California, Santa Cruz, USA

  Matthew Guthaus

• University of South Florida, Tampa, USA

  Srinivas Katkoori

• Instituto de Informática, Universidade Federal do Rio Grande do Sul, Porto Alegre, Brazil

  Ricardo Reis

Policies and ethics