Transactions on High-Performance Embedded Architectures and Compilers IV

1. Front Matter

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2. Regular Papers

   1. A High Performance Adaptive Miss Handling Architecture for Chip Multiprocessors

      • Magnus Jahre, Lasse Natvig

      Pages 1-20

   2. Characterizing Time-Varying Program Behavior Using Phase Complexity Surfaces

      • Frederik Vandeputte, Lieven Eeckhout

      Pages 21-41

   3. Compiler Directed Issue Queue Energy Reduction

      • Timothy M. Jones, Michael F. P. O’Boyle, Jaume Abella, Antonio González

      Pages 42-62

   4. A Systematic Design Space Exploration Approach to Customising Multi-Processor Architectures: Exemplified Using Graphics Processors

      • Ben Cope, Peter Y. K. Cheung, Wayne Luk, Lee Howes

      Pages 63-83

   5. Microvisor: A Runtime Architecture for Thermal Management in Chip Multiprocessors

      • Omer Khan, Sandip Kundu

      Pages 84-110

3. 4th International Conference on High-Performance and Embedded Architectures and Compilers – HiPEAC (Selected Papers)

   1. A Highly Scalable Parallel Implementation of H.264

      • Arnaldo Azevedo, Ben Juurlink, Cor Meenderinck, Andrei Terechko, Jan Hoogerbrugge, Mauricio Alvarez et al.

      Pages 111-134

   2. Communication Based Proactive Link Power Management

      • Sai Prashanth Muralidhara, Mahmut Kandemir

      Pages 135-154

   3. Finding Extreme Behaviors in Microprocessor Workloads

      • Frederik Vandeputte, Lieven Eeckhout

      Pages 155-174

   4. Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture

      • Michael B. Henry, Leyla Nazhandali

      Pages 175-194

4. Workshop on Software and Hardware Challenges of Many-core Platforms – SHCMP (Selected Papers)

   1. Transaction Reordering to Reduce Aborts in Software Transactional Memory

      • Mohammad Ansari, Mikel Luján, Christos Kotselidis, Kim Jarvis, Chris Kirkham, Ian Watson

      Pages 195-214

   2. A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture

      • Yasutaka Wada, Akihiro Hayashi, Takeshi Masuura, Jun Shirako, Hirofumi Nakano, Hiroaki Shikano et al.

      Pages 215-233

   3. A Modular Simulator Framework for Network-on-Chip Based Manycore Chips Using UNISIM

      • Xiongfei Liao, Wu Jigang, Thambipillai Srikanthan

      Pages 234-253

   4. Software Transactional Memory Validation – Time and Space Considerations

      • Adam Welc, Bratin Saha

      Pages 254-273

   5. Tiled Multi-Core Stream Architecture

      • Nan Wu, Qianming Yang, Mei Wen, Yi He, Ju Ren, Maolin Guan et al.

      Pages 274-293

   6. An Efficient and Flexible Task Management for Many Cores

      • Yuan Nan, Yu Lei, Fan Dong-rui

      Pages 294-310

5. 8th IEEE International Symposium on Systems, Architectures, Modeling and Simulation – SAMOS VIII (Selected Papers)

   1. On Two-Layer Brain-Inspired Hierarchical Topologies – A Rent’s Rule Approach –

      • Valeriu Beiu, Basheer A. M. Madappuram, Peter M. Kelly, Liam J. McDaid

      Pages 311-333

   2. Advanced Packet Segmentation and Buffering Algorithms in Network Processors

      • Daniel Llorente, Kimon Karras, Thomas Wild, Andreas Herkersdorf

      Pages 334-353

   3. Energy Reduction by Systematic Run-Time Reconfigurable Hardware Deactivation

      • W. G. Osborne, W. Luk, J. G. F. Coutinho, O. Mencer

      Pages 354-369

   4. A Cost Model for Partial Dynamic Reconfiguration

      • Markus Rullmann, Renate Merker

      Pages 370-390

Transactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performance embedded computer systems. Recognizing the convergence of embedded and general-purpose computer systems, this journal publishes original research on systems targeted at specific computing tasks as well as systems with broad application bases. The scope of the journal therefore covers all aspects of computer architecture, code generation and compiler optimization methods of interest to researchers and practitioners designing future embedded systems. This 4th issue contains 21 papers carefully reviewed and selected out of numerous submissions and is divided in four sections. The first section contains five regular papers. The second section consists of the top four papers from the 4th International Conference on High-Performance Embedded Architectures and Compilers, HiPEAC 2009, held in Paphos, Cyprus, in January 2009. The third section contains a set of six papers providing a snap-shot from the Workshop on Software and Hardware Challenges of Manycore Platforms, SHCMP 2008 held in Beijing, China, in June 2008. The fourth section consists of six papers from the 8th IEEE International Symposium on Systems, Architectures, Modeling and Simulation, SAMOS VIII (2008) held in Samos, Greece, in July 2008.

• chip multiprocessing
• evolutionary multiobjective optimization
• many-core architecture
• network-on-chip
• signal processing

• Department of Computer Science and Engineering, Chalmers University of Technology, Gothenburg, Sweden

  Per Stenström

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