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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

21st International Workshop, PATMOS 2011, Madrid, Spain, September 26-29, 2011, Proceedings

  • Conference proceedings
  • © 2011

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Editors:
  1. José L. Ayala

    1. Universidad Complutense de Madrid, Spain

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  2. Braulio García-Cámara

    1. Universidad de Cantabria, Santander, Spain

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  3. Manuel Prieto

    1. Universidad Complutense de Madrid, Spain

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  4. Martino Ruggiero

    1. Università di Bologna, Italy

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  5. Gilles Sicard

    1. TIMA Laboratory, Grenoble, France

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Part of the book series: Lecture Notes in Computer Science (LNCS, volume 6951)

Part of the book sub series: Theoretical Computer Science and General Issues (LNTCS)

Included in the following conference series:

Conference proceedings info: PATMOS 2011.

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Table of contents (34 papers)

  1. Front Matter

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  2. A Quick Method for Energy Optimized Gate Sizing of Digital Circuits

    • Mustafa Aktan, Dursun Baran, Vojin G. Oklobdzija
    Pages 1-10

  3. Power Profiling-Guided Floorplanner for Thermal Optimization in 3D Multiprocessor Architectures

    • Ignacio Arnaldo, José L. Risco-Martín, José L. Ayala, J. Ignacio Hidalgo
    Pages 11-21

  4. A System Level Approach to Multi-core Thermal Sensors Calibration

    • Andrea Bartolini, MohammadSadegh Sadri, Francesco Beneventi, Matteo Cacciari, Andrea Tilli, Luca Benini
    Pages 22-31

  5. Improving the Robustness of Self-timed SRAM to Variable Vdds

    • Abdullah Baz, Delong Shang, Fei Xia, Alex Yakovlev, Alex Bystrov
    Pages 32-42

  6. Architecture Extensions for Efficient Management of Scratch-Pad Memory

    • José V. Busquets-Mataix, Carlos Catalá, Antonio Martí-Campoy
    Pages 43-52

  7. Pass Transistor Operation Modeling for Nanoscale Technologies

    • Panagiotis Chaourani, Ilias Pappas, Spiros Nikolaidis, Abdoul Rjoub
    Pages 53-62

  8. Timing Modeling of Flipflops Considering Aging Effects

    • Ning Chen, Bing Li, Ulf Schlichtmann
    Pages 63-72

  9. Iterative Timing Analysis Considering Interdependency of Setup and Hold Times

    • Ning Chen, Bing Li, Ulf Schlichtmann
    Pages 73-82

  10. Ultra Compact Non-volatile Flip-Flop for Low Power Digital Circuits Based on Hybrid CMOS/Magnetic Technology

    • Gregory Di Pendina, Kholdoun Torki, Guillaume Prenat, Yoann Guillemenet, Lionel Torres
    Pages 83-91

  11. Performance-Driven Clustering of Asynchronous Circuits

    • Georgios D. Dimou, Peter A. Beerel, Andrew M. Lines
    Pages 92-101

  12. Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal Processing

    • Ahmed Yasir Dogan, David Atienza, Andreas Burg, Igor Loi, Luca Benini
    Pages 102-111

  13. Agent-Based Thermal Management Using Real-Time I/O Communication Relocation for 3D Many-Cores

    • Thomas Ebi, Holm Rauchfuss, Andreas Herkersdorf, Jörg Henkel
    Pages 112-121

  14. Energy Estimator for Weather Forecasts Dynamic Power Management of Wireless Sensor Networks

    • Nicolas Ferry, Sylvain Ducloyer, Nathalie Julien, Dominique Jutel
    Pages 122-132

  15. Self-reference Scrubber for TMR Systems Based on Xilinx Virtex FPGAs

    • Ignacio Herrera-Alzu, Marisa López-Vallejo
    Pages 133-142

  16. Cell-Based Leakage Power Reduction Priority (CBLPRP) Optimization Methodology for Designing SOC Applications Using MTCMOS Technique

    • Henry X. F. Huang, Steven R. S. Shen, James B. Kuo
    Pages 143-151

  17. NBTI Mitigation by Giving Random Scan-in Vectors during Standby Mode

    • Toshihiro Kameda, Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye
    Pages 152-161

  18. An On-Chip All-Digital PV-Monitoring Architecture for Digital IPs

    • Hossein Karimiyan, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino
    Pages 162-172

  19. Chip Level Statistical Leakage Power Estimation Using Generalized Extreme Value Distribution

    • Alireza Khosropour, Hossein Aghababa, Ali Afzali-Kusha, Behjat Forouzandeh
    Pages 173-179

  20. Using Silent Writes in Low-Power Traffic-Aware ECC

    • Mostafa Kishani, Amirali Baniasadi, Hossein Pedram
    Pages 180-192
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Other volumes

  1. Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation

Keywords

About this book

This book constitutes the refereed proceedings of the 21st International Conference on Integrated Circuit and System Design, PATMOS 2011, held in Madrid, Spain, in September 2011. The 34 revised full papers presented were carefully reviewed and selected from numerous submissions. The paper feature emerging challenges in methodologies and tools for the design of upcoming generations of integrated circuits and systems and focus especially on timing, performance and power consumption as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and optimization.

Editors and Affiliations

  • Universidad Complutense de Madrid, Spain

    José L. Ayala, Manuel Prieto

  • Universidad de Cantabria, Santander, Spain

    Braulio García-Cámara

  • Università di Bologna, Italy

    Martino Ruggiero

  • TIMA Laboratory, Grenoble, France

    Gilles Sicard

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