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Formal Methods in Computer-Aided Design

Second International Conference, FMCAD '98, Palo Alto, CA, USA, November 4-6, 1998, Proceedings

  • Conference proceedings
  • © 1998

Overview

Editors:
  1. Ganesh Gopalakrishnan

    1. Department of Computer Science, University of Utah, Salt Lake City, USA

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    You can also search for this editor in PubMed   Google Scholar

  2. Phillip Windley

    1. Department of Computer Science, Brigham Young University, Provo, USA

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    You can also search for this editor in PubMed   Google Scholar

Part of the book series: Lecture Notes in Computer Science (LNCS, volume 1522)

Included in the following conference series:

Conference proceedings info: FMCAD 1998.

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Table of contents (35 papers)

  1. Front Matter

    Pages I-IX
    Download chapter PDF

  2. Minimalist Proof Assistants: Interactions of Technology and Methodology in Formal System Level Verification

    • Kenneth L. McMillan
    Pages 1-1

  3. Reducing Manual Abstraction in Formal Verification of Out- of- Order Execution

    • Robert B. Jones, Jens U. SkakkebÆk, David L. Dill
    Pages 2-17

  4. Bit-Level Abstraction in the Verification of Pipelined Microprocessors by Correspondence Checking

    • Miroslav N. Velev, Randal E. Bryant
    Pages 18-35

  5. Solving Bit-Vector Equations

    • M. Oliver Möller, Harald Rue\
    Pages 36-48

  6. The Formal Design of 1M-Gate ASICs

    • ásgeir þór Eiríksson
    Pages 49-63

  7. Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations

    • Justin E. Harlow III, Franc Brglez
    Pages 64-81

  8. A Tutorial on Stålmarck’s Proof Procedure for Propositional Logic

    • Mary Sheeran, Gunnar Stålmarck
    Pages 82-99

  9. Almana: A BDD Minimization Tool Integrating Heuristic and RewritingMethods

    • Macha NikolskaÏa, Antoine Rauzy, David James Sherman
    Pages 100-114

  10. Bisimulation Minimization in an Automata-Theoretic Verification Framework

    • Kathi Fisler, Moshe Y. Vardi
    Pages 115-132

  11. Automatic Verification of Mixed-Level Logic Circuits

    • Keith Hanna
    Pages 133-148

  12. A Timed Automaton-Based Method for Accurate Computation of Circuit Delay in the Presence of Cross-Talk

    • S. Ta§iran, S. P. Khatri, S. Yovine, R. K. Brayton, A. Sangiovanni-Vincentelli
    Pages 149-166

  13. Maximum Time Separation of Events in Cyclic Systems with Linear and Latest Timing Constraints

    • Fen Jin, Henrik Hulgaard, Eduard Cerny
    Pages 167-184

  14. Using MTBDDs for Composition and Model Checking of Real-Time Systems

    • Jürgen Ruf, Thomas Kropf
    Pages 185-202

  15. Formal Methods in CAD from an Industrial Perspective

    • Carl-Johan H. Seger
    Pages 203-203

  16. A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool

    • Nazanin Mansouri, Ranga Vemuri
    Pages 204-221

  17. Combined Formal Post- and Presynthesis Verification in High Level Synthesis

    • Thomas Lock, Michael Mendler, Matthias Mutz
    Pages 222-236

  18. Formalization and Proof of a Solution to the PCI 2.1 Bus Transaction Ordering Problem

    • Abdel Mokkedem, Ravi Hosabettu, Ganesh Gopalakrishnan
    Pages 237-254

  19. A Performance Study of BDD-Based Model Checking

    • Bwolen Yang, Randal E. Bryant, David R. O’Hallaron, Armin Biere, Olivier Coudert, Geert Janssen et al.
    Pages 255-289

  20. Symbolic Model Checking Visualization

    • Gila Kamhi, Limor Fix, Ziv Binyamini
    Pages 290-302
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  1. Formal Methods in Computer-Aided Design

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Editors and Affiliations

  • Department of Computer Science, University of Utah, Salt Lake City, USA

    Ganesh Gopalakrishnan

  • Department of Computer Science, Brigham Young University, Provo, USA

    Phillip Windley

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