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Field-Programmable Logic: Architectures, Synthesis and Applications

4th International Workshop on Field-Programmable Logic and Applications, FPL'94, Prague, Czech Republic, September 7 - 9, 1994. Proceedings

  • Conference proceedings
  • © 1994

Overview

Editors:
  1. Reiner W. Hartenstein
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  2. Michal Z. Servít
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Part of the book series: Lecture Notes in Computer Science (LNCS, volume 849)

Included in the following conference series:

Conference proceedings info: FPL 1994.

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Table of contents (63 papers)

  1. Front Matter

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  2. Fault modeling and test generation for FPGAs

    • Michael Hermann, Wolfgang Hoffmann
    Pages 1-10

  3. A test methodology applied to Cellular logic Programmable Gate Arrays

    • Ricardo de O. Duarte, Mihaîl Nicolaidis
    Pages 11-22

  4. Integrated layout synthesis for FPGA's

    • Michal Z. Servít, Zdeněk Muzikář
    Pages 23-33

  5. Influence of logic block layout architecture on FPGA performance

    • M. Robert, L. Torres, F. Moraes, D. Auvergne
    Pages 34-44

  6. A global routing heuristic for FPGAs based on mean field annealing

    • Ismail Haritaoğlu, Cevdet Aykanat
    Pages 45-56

  7. Power dissipation driven FPGA place and route under delay constraints

    • Kaushik Roy, Sharat Prasad
    Pages 57-65

  8. FPGA technology mapping for power minimization

    • Amir H. Farrahi, Majid Sarrafzadeh
    Pages 66-77

  9. Specification and synthesis of complex arithmetic operators for FPGAs

    • Hans-Juergen Brand, Dietmar Mueller, Wolfgang Rosenstiel
    Pages 78-88

  10. A speed-up technique for synchronous circuits realized as LUT-based FPGAs

    • Toshiaki Miyazaki, Hiroshi Nakada, Akihiro Tsutsui, Kazuhisa Yamada, Naohisa Ohta
    Pages 89-92

  11. An efficient technique for mapping RTL structures onto FPGAs

    • A. R. Naseer, M. Balakrishnan, Anshul Kumar
    Pages 99-110

  12. A testbench design method suitable for FPGA-based prototyping of reactive systems

    • Volker Hamann
    Pages 111-113

  13. Using consensusless covers for fast operating on Boolean functions

    • Eugene Goldberg, Ludmila Krasilnikova
    Pages 114-116

  14. Formal verification of timing rules in design specifications

    • Tibor Bartos, Norbert Fristacky
    Pages 117-119

  15. Optimized synthesis of self-testable finite state machines (FSM) using BIST-PST structures in Altera structures

    • Andrzej Hlawiczka, IEEE, Jacek Binda
    Pages 120-122

  16. A high-speed rotation processor

    • Jan Lichtermann, Günter Neustädter
    Pages 123-125

  17. The MD5 message-digest algorithm in the XILINX FPGA

    • P. Gramata, P. Trebatický, E. Gramatová
    Pages 126-128

  18. A reprogrammable processor for fractal image compression

    • Barry Fagin, Pichet Chintrakulchai
    Pages 129-131

  19. Implementing GCD systolic Arrays on FPGA

    • Tudor Jebelean
    Pages 132-134

  20. Formal CAD techniques for safety-critical FPGA design and deployment in embedded subsystems

    • R. B. Hughes, G. Musgrave
    Pages 135-137
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Other volumes

  1. Field-Programmable Logic Architectures, Synthesis and Applications

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About this book

This volume contains the proceedings of the 4th International Workshop on Field-Programmable Logic and Applications (FPL '94), held in Prague, Czech Republic in September 1994. The growing importance of field-programmable devices is substantiated by the remarkably high number of 116 submissions for FPL '94; from them, the revised versions of 40 full papers and 24 high-quality poster presentations were accepted for inclusion in this volume. Among the topics treated are: testing, layout, synthesis tools, compilation research and CAD, trade-offs and experience, innovations and smart applications, FPGA-based computer architectures, high-level design, prototyping and ASIC emulators, commercial devices, new tools, CCMs and HW/SW co-design, modelers, educational experience, and novel architectures.

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