Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation

1. Front Matter

   Pages I-XVI

   PDF

2. Opening

   1. The First Quartz Electronic Watch

      • Christian Piguet

      Pages 1-15

3. Arithmetics

   1. An Improved Power Macro-Model for Arithmetic Datapath Components

      • D. Helms, E. Schmidt, A. Schulz, A. Stammermann, W. Nebel

      Pages 16-24

   2. Performance Comparison of VLSI Adders Using Logical Effort

      • Hoang Q. Dao, Vojin G. Oklobdzija

      Pages 25-34

   3. MDSP: A High-Performance Low-Power DSP Architecture

      • F. Pessolano, J. Kessels, A. Peeters

      Pages 35-44

4. Low-Level Modeling and Characterization

   1. Impact of Technology in Power-Grid-Induced Noise

      • Juan-Antonio Carballo, Sani R. Nassif

      Pages 45-54

   2. Exploiting Metal Layer Characteristics for Low-Power Routing

      • Armin Windschiegl, Paul Zuber, Walter Stechele

      Pages 55-64

   3. Crosstalk Measurement Technique for CMOS ICs

      • F. Picot, P. Coll, D. Auvergne

      Pages 65-70

   4. Instrumentation Set-up for Instruction Level Power Modeling

      • S. Nikolaidis, N. Kavvadias, P. Neofotistos, K. Kosmatopoulos, T. Laopoulos, L. Bisdounis

      Pages 71-80

5. Asynchronous and Adiabatic Techniques

   1. Low-Power Asynchronous A/D Conversion

      • Emmanuel Allier, Laurent Fesquet, Marc Renaudin, Gilles Sicard

      Pages 81-91

   2. Optimal Two-Level Delay — Insensitive Implementation of Logic Functions

      • Igor Lemberski, Mark Josephs

      Pages 92-100

   3. Resonant Multistage Charging of Dominant Capacitances

      • Christoph Saas, Josef A. Nossek

      Pages 101-107

   4. A New Methodology to Design Low-Power Asynchronous Circuits

      • Oscar Garnica, Juan Lanchares, Román Hermida

      Pages 108-117

   5. Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Library

      • Antonio Blotti, Maurizio Castellucci, Roberto Saletti

      Pages 118-127

6. CAD Tools and Algorithms

   1. Clocking and Clocked Storage Elements in Multi-GHz Environment

      • Vojin G. Oklobdzija

      Pages 128-145

   2. Dual Supply Voltage Scaling in a Conventional Power-Driven Logic Synthesis Environment

      • Torsten Mahnke, Walter Stechele, Wolfgang Hoeld

      Pages 146-155

   3. Transistor Level Synthesis Dedicated to Fast I.P. Prototyping

      • A. Landrault, L. Pellier, A. Richard, C. Jay, M. Robert, D. Auvergne

      Pages 156-166

   4. Robust SAT-Based Search Algorithm for Leakage Power Reduction

      • Fadi A. Aloul, Soha Hassoun, Karem A. Sakallah, David Blaauw

      Pages 167-177

7. Timing

   1. PA-ZSA (Power-Aware Zero-Slack Algorithm): A Graph-Based Timing Analysis for Ultra-Low Power CMOS VLSI

      • Kyu-won Choi, Abhijit Chatterjee

      Pages 178-187

   2. A New Methodology for Efficient Synchronization of RNS-Based VLSI Systems

      • Daniel González, Antonio García, Graham A. Jullien, Javier Ramírez, Luis Parrilla, Antonio Lloris

      Pages 188-197

The International Workshop on Power and Timing Modeling, Optimization, and Simulation PATMOS 2002, was the 12th in a series of international workshops 1 previously held in several places in Europe. PATMOS has over the years evolved into a well-established and outstanding series of open European events on power and timing aspects of integrated circuit design. The increased interest, espe- ally in low-power design, has added further momentum to the interest in this workshop. Despite its growth, the workshop can still be considered as a very - cused conference, featuring high-level scienti?c presentations together with open discussions in a free and easy environment. This year, the workshop has been opened to both regular papers and poster presentations. The increasing number of worldwide high-quality submissions is a measure of the global interest of the international scienti?c community in the topics covered by PATMOS. The objective of this workshop is to provide a forum to discuss and inves- gate the emerging problems in the design methodologies and CAD-tools for the new generation of IC technologies. A major emphasis of the technical program is on speed and low-power aspects with particular regard to modeling, char- terization, design, and architectures. The technical program of PATMOS 2002 included nine sessions dedicated to most important and current topics on power and timing modeling, optimization, and simulation. The three invited talks try to give a global overview of the issues in low-power and/or high-performance circuit design.

• algorithm
• communication
• integrated circuit
• modeling
• optimization
• simulation
• tools

• Ecole d’Ingénieurs du Canton de Vaud Microelectronics and Systems Institute, Digital Communications Team, Swiss University of Applied Science, Yverdon, Switzerland

  Bertrand Hochet

• Instituto de Microelectrónica de Sevilla-CNM-CSIC Departamento do Diseño Digital Departamento de Electrónica y Electromagnetismo Departamento de Tecnología Electrónica, Universidad de Sevilla

  Antonio J. Acosta, Manuel J. Bellido

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