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Correct Hardware Design and Verification Methods

IFIP WG10.5 Advanced Research Working Conference, CHARME '95, Frankfurt, Germany, October 1995. Proceedings

  • Conference proceedings
  • © 1995

Overview

Editors:
  1. Paolo E. Camurati
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  2. Hans Eveking
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Part of the book series: Lecture Notes in Computer Science (LNCS, volume 987)

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Table of contents (20 papers)

  1. Front Matter

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  2. What if model checking must be truly symbolic

    • Hardi Hungar, Orna Grumberg, Werner Damm
    Pages 1-20

  3. Automatic verification of the SCI cache coherence protocol

    • Ulrich Stern, David L. Dill
    Pages 21-34

  4. Describing and verifying synchronous circuits with the Boyer-Moore theorem prover

    • Laurence Pierre
    Pages 35-55

  5. Problems encountered in the machine-assisted proof of hardware

    • Paul Curzon
    Pages 56-70

  6. Formally embedding existing high level synthesis algorithms

    • Dirk Eisenbiegler, Ramayya Kumar
    Pages 71-83

  7. Formal design of a class of computers — its high stage: abstract microprogramming

    • Li -Guo Wang, Michael Mendler
    Pages 84-102

  8. Symbolic analysis and verification of CPA descriptions

    • M. C. McFarland, T. J. Kowalski
    Pages 103-123

  9. A foundation for formal reuse of hardware

    • Ana C. V. de Melo, Howard Barringer
    Pages 124-145

  10. State enumeration with abstract descriptions of state machines

    • F. Corella, M. Langevin, E. Cerny, Z. Zhou, X. Song
    Pages 146-160

  11. Transforming Boolean relations by symbolic encoding

    • Gianpiero Cabodi, Stefano Quer, Paolo Camurati
    Pages 161-170

  12. Design error diagnosis in sequential circuits

    • Ayman Wahba, Dominique Borrione
    Pages 171-188

  13. Timing analysis of asynchronous circuits using timed automata

    • Oded Maler, Amir Pnueli
    Pages 189-205

  14. Improved probabilistic verification by hash compaction

    • Ulrich Stern, David L. Dill
    Pages 206-224

  15. Formal support for the ELLA hardware description language

    • Howard Barringer, Graham Gough, Brian Monahan, Alan Williams
    Pages 225-245

  16. Verifying hardware components with JACK

    • R. De Nicola, A. Fantechi, S. Gnesi, S. Larosa, G. Ristori
    Pages 246-260

  17. Language containment of non-deterministic Ω-automata

    • Serdar TaÅžiran, Ramin Hojati, Robert K. Brayton
    Pages 261-277

  18. A partial-order approach to the verification of concurrent systems: Checking liveness properties

    • Dominique Bolignano
    Pages 278-292

  19. Semantics of a verification-oriented subset of VHDL

    • David Déharbe, Dominique Borrione
    Pages 293-310

  20. Reasoning about VHDL using operational and observational semantics

    • K. G. W. Goossens
    Pages 311-327
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Keywords

About this book

This book constitutes the refereed proceedings of the IFIP WG10.5 Advanced Research Working Conference on Correct Hardware Design Methodologies, CHARME '95, held in Frankfurt, Germany, in October 1995.
The 20 revised full papers presented were carefully selected by the program committee and address all current aspects of research and advanced applications in the field of formal verification of hardware. Among the topics covered are model checking, theorem proving, formally verified synthesis, process algebras, finite state systems, verification environments, language containment, and VHDL.

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