Correct Hardware Design and Verification Methods

1. Front Matter

   Pages I-XI

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2. Invited Contributions

   1. View from the Fringe of the Fringe

      • Steven D. Johnson

      Pages 1-12

   2. Hardware Synthesis Using SAFL and Application to Processor Design

      • Alan Mycroft, Richard Sharp

      Pages 13-39

3. FMCAD 2000

   1. Applications of Hierarchical Verification in Model Checking

      • Robert Beers, Rajnish Ghughal, Mark Aagaard

      Pages 40-57

4. Model Checking 1

   1. Pruning Techniques for the SAT-Based Bounded Model Checking Problem

      • Ofer Shtrichman

      Pages 58-70

   2. Heuristics for Hierarchical Partitioning with Application to Model Checking

      • M. Oliver Möller, Rajeev Alur

      Pages 71-85

5. Short Papers 1

   1. Efficient Reachability Analysis and Refinement Checking of Timed Automata Using BDDs

      • Dirk Beyer

      Pages 86-91

   2. Deriving Real-Time Programs from Duration Calculus Specifications

      • François Siewe, Dang Van Hung

      Pages 92-97

   3. Reproducing Synchronization Bugs with Model Checking

      • Karen Yorav, Sagi Katz, Ron Kiper

      Pages 98-103

   4. Formally-Based Design Evaluation

      • Kenneth J. Turner, Ji He

      Pages 104-109

6. Clocking Issues

   1. Multiclock Esterel

      • Gérard Berry, Ellen Sentovich

      Pages 110-125

   2. Register Transformations with Multiple Clock Domains

      • Alvin R. Albrecht, Alan J. Hu

      Pages 126-139

   3. Temporal Properties of Self-Timed Rings

      • Anthony Winstanley, Mark Greenstreet

      Pages 140-154

7. Short Papers 2

   1. Coverability Analysis Using Symbolic Model Checking

      • Gil Ratzaby, Shmuel Ur, Yaron Wolfsthal

      Pages 155-160

   2. Specifying Hardware Timing with ET-Lotos

      • Ji He, Kenneth J. Turner

      Pages 161-166

   3. Formal Pipeline Design

      • Tiberiu Seceleanu, Juha Plosila

      Pages 167-172

   4. Verification of Basic Block Schedules Using RTL Transformations

      • Rajesh Radhakrishnan, Elena Teica, Ranga Vemuri

      Pages 173-178

8. Joint Session with TPHOLs

   1. Parameterized Verification of the FLASH Cache Coherence Protocol by Compositional Model Checking

      • K. L. McMillan

      Pages 179-195

   2. Proof Engineering in the Large: Formal Verification of Pentium®4 Floating-Point Divider

      • Roope Kaivola, Katherine Kohatsu

      Pages 196-211

9. Hardware Compilation

   1. Towards Provably-Correct Hardware Compilation Tools Based on Pass Separation Techniques

      • Steve McKeever, Wayne Luk

      Pages 212-227

This volume contains the proceedings of CHARME 2001, the Eleventh Advanced Research Working Conference on Correct Hardware Design and Veri?cation Methods. CHARME 2001 is the 11th in a series of working conferences devoted to the development and use of leading-edge formal techniques and tools for the design and veri?cation of hardware and hardware-like systems. Previous events in the ‘CHARME’ series were held in Bad Herrenalb (1999), Montreal (1997), Frankfurt (1995), Arles (1993), and Torino (1991). This series of meetings has been organized in cooperation with IFIP WG 10.5 and WG 10.2. Prior meetings, stretching backto the earliest days of formal hardware veri?cation, were held under various names in Miami (1990), Leuven (1989), Glasgow (1988), Grenoble (1986), Edinburgh (1985), and Darmstadt (1984). The convention is now well-established whereby the European CHARME conference alternates with its biennial counterpart, the International Conference on Formal Methods in Computer-Aided Design (FMCAD), which is held on even-numbered years in the USA. The conference tookplace during 4–7 September 2001 at the Institute for System Level Integration in Livingston, Scotland. It was co-hosted by the - stitute and the Department of Computing Science of Glasgow University and co-sponsored by the IFIP TC10/WG10.5 Working Group on Design and En- neering of Electronic Systems. CHARME 2001 also included a scienti?c session and social program held jointly with the 14th International Conference on Th- rem Proving in Higher Order Logics (TPHOLs), which was co-located in nearby Edinburgh.

• Clocking
• Hardware
• algorithm
• algorithms
• design
• model
• model checking
• proving
• theorem proving
• verification

• Lehrstuhl für Programmiersysteme, Universität Dortmund, Dortmund, Germany

  Tiziana Margaria

• Department of Computing Science, University of Glasgow, Glasgow, UK

  Tom Melham

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