Artificial Neural Nets. Problem Solving Methods

Nets Design

1. FPGA Implementation of a Perceptron-like Neural Network for Embedded Applications

   • Eva M. Ortigosa, Antonio Cañas, Eduardo Ros, Richard R. Carrillo

   Pages 1-8

2. NSP: a Neuro–Symbolic Processor

   • Ernesto Burattini, Massimo De Gregorio, Victor M. G. Ferreira, Felipe M. G. França

   Pages 9-16

3. Reconfigurable Hardware Architecture for Compact and Efficient Stochastic Neuron

   • Nadia Nedjah, Luiza de Macedo Mourelle

   Pages 17-24

4. Current mode CMOS synthesis of a motor–control neural system

   • Ginés Doménech-Asensi, Ramón Ruiz-Merino, Hans Hauer, José Ángel Díaz-Madrid

   Pages 25-32

5. New emulated discrete model of CNN architecture for FPGA and DSP applications

   • Martínez J.J., Toledo F.J., Ferrández J.M.

   Pages 33-40

6. A Binary Multiplier Using RTD Based Threshold Logic Gates

   • P M Kelly, C J Thompson, T M McGinnity, L P Maguire

   Pages 41-48

7. Split-Precharge Differential Noise-Immune Threshold Logic Gate (SPD-NTL)

   • Suryanarayana Tatapudi, Valeriu Beiu

   Pages 49-56

8. UV-programmable Floating-Gate CMOS Linear Threshold Element ”P1N3”

   • Snorre Aunet, Yngvar Berg

   Pages 57-64

9. CMOS Implementation of Generalized Threshold Functions

   • Marius Padure, Sorin Cotofana, Stamatis Vassiliadis

   Pages 65-72

10. A-DELTA: A 64-bit High Speed, Compact, Hybrid Dynamic-CMOS/Threshold-Logic Adder

    • Peter Celinski, Sorin D. Cotofana, Derek Abbott

    Pages 73-80

11. Validation of a Cortical Electrode Model for Neuroprosthetics purposes

    • García-de-Quirós F.J, Bonomini M.P., Ferrández J.M., Fernández E.

    Pages 81-88

12. XMLP: a Feed-Forward Neural Network with Two-Dimensional Layers and Partial Connectivity

    • Antonio Canas, Eva M. Ortigosa, Antonio F. Díaz, Julio Ortega

    Pages 89-96

13. An analogue current–mode hardware design proposal for preprocessing layers in ART-based neural networks

    • José-Alejandro López Alcantud, José-Ángel Díaz Madrid, Hans Hauer, Ramón Ruiz Merino

    Pages 97-104

14. On the effects of dimensionality on data analysis with neural networks

    • M. Verleysen, D. Francois, G. Simon, V. Wertz

    Pages 105-112

15. Hardware Optimization of a Novel Spiking Neuron Model for the POEtic tissue.

    • Oriol Torres, Jan Eriksson, Juan Manuel Moreno, Alessandro Villa

    Pages 113-120

16. Implementing a Margolus Neighborhood Cellular Automata on a FPGA

    • Joaquín Cerda, Rafael Gadea, Guillermo Paya

    Pages 121-128

17. An Empirical Comparison of Training Algorithms for Radial Basis Functions

    • Mamen Ortiz-Gómez, Carlos Hernández-Espinosa, Mercedes Fernández-Redondo

    Pages 129-136

18. Ensemble Methods for Multilayer Feedforward: An Experimental Study

    • Carlos Hernández-Espinosa, Mercedes Fernández-Redondo, Mamen Ortiz-Gómez

    Pages 137-144

19. Post-synaptic Time-dependent Conductances in Spiking Neurons: FPGA Implementation of a Flexible Cell Model

    • Eduardo Ros, Rodrigo Agis, Richard R. Carrillo, Eva M. Ortigosa

    Pages 145-152