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High Performance Computing

Third International Symposium, ISHPC 2000 Tokyo, Japan, October 16-18, 2000 Proceedings

  • Conference proceedings
  • © 2000

Overview

Editors:
  1. Mateo Valero

    1. Departamento de Arquitectura de Computadores, Universidad Politecnica de Catalunya, Spain

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  2. Kazuki Joe

    1. Department of Information and Computer Sciences, Nara Women’s University, Japan

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  3. Masaru Kitsuregawa

    1. Institute of Industrial Science Center for Conceptual Information Processing Research, University of Tokyo, Japan

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  4. Hidehiko Tanaka

    1. Graduate School of Engineering Electrical Engineering Department, University of Tokyo, Japan

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Part of the book series: Lecture Notes in Computer Science (LNCS, volume 1940)

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Table of contents (56 papers)

  1. Front Matter

    Pages I-XV
    Download chapter PDF

  2. Invited Papers

    1. Instruction Level Distributed Processing: Adapting to Future Technology

      • J. E. Smith
      Pages 1-6

    2. Macroservers: An Object-Based Programming and Execution Model for Processor-in-Memory Arrays

      • Hans P. Zima, Thomas L. Sterling
      Pages 7-25

    3. The New DRAM Interfaces: SDRAM, RDRAM and Variants

      • Brian Davis, Bruce Jacob, Trevor Mudge
      Pages 26-31

    4. Blue Gene

      • Henry S. Warren Jr.
      Pages 32-32

    5. Earth Simulator Project in Japan

      • Keiji Tani
      Pages 33-42

  3. Compilers, Architectures and Evaluation

    1. Limits of Task-based Parallelism in Irregular Applications

      • Barbara Kreaseck, Dean Tullsen, Brad Calder
      Pages 43-58

    2. The Case for Speculative Multithreading on SMT Processors

      • Haitham Akkary, Sébastien Hily
      Pages 59-72

    3. Loop Termination Prediction

      • Timothy Sherwood, Brad Calder
      Pages 73-87

    4. Compiler-Directed Cache Assist Adaptivity

      • Xiaomei Ji, Dan Nicolaescu, Alexander Veidenbaum, Alexandru Nicolau, Rajesh Gupta
      Pages 88-104

    5. Skewed Data Partition and Alignment Techniques for Compiling Programs on Distributed Memory Multicomputers

      • Tzung-Shi Chen, Chih-Yung Chang
      Pages 105-119

    6. Processor Mechanisms for Software Shard Memory

      • Nicholas P., William J., Whay S., Stephen W. Keckler, Andrew Chang
      Pages 120-133

    7. An Evaluation of Page Aggregation Technique on Different DSM Systems

      • Mario Donato, Geraldo Lino
      Pages 134-145

    8. Nanothreads vs. Fibers for the Support of Fine Grain Parallelism on Windows NT/2000 Platforms

      • Vasileios K. Barekas, Panagiotis E. Hadjidoukas, Eleftherios D. Polychronopoulos, Theodore S. Papatheodorou
      Pages 146-159

  4. Algorithms, Models and Applications

    1. Partitioned Parallel Radix Sort

      • Shin-Jae Lee, Minsoo Jeon, Andrew Sohn, Dongseung Kim
      Pages 160-171

    2. Transonic Wing Shape Optimization Based on Evolutionary Algorithms

      • Shigeru Obayashi, Akira Oyama, Takashi Nakamura
      Pages 172-181

    3. A Common CFD Platform UPACS

      • Hiroyuki Yamazaki, Shunji Enomoto, Kazuomi Yamamoto
      Pages 182-190

    4. On Performance Modeling for HPF Applications with ASL

      • Thomas Fahringer, Michael Gerndt, Graham Riley, Jesper Larsson Träff
      Pages 191-204

    5. A “Generalized k-Tree-Based Model to Sub-system Allocation” for Partitionable Multi-dimensional Mesh-Connected Architectures

      • Jeeraporn Srisawat, Nikitas Alexandridis A.
      Pages 205-217

    6. An Analytic Model or Communication Latency in Wormhole-Switched k -Ary n -Cube Interconnection Networks with Digit-Reversal Traffic

      • H. Sarbazi-Azad, L.M. Mackenzie, M. Ould-Khaoua
      Pages 218-229
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Keywords

About this book

I wish to welcome all of you to the International Symposium on High Perf- mance Computing 2000 (ISHPC 2000) in the megalopolis of Tokyo. After having two great successes with ISHPC’97 (Fukuoka, November 1997) and ISHPC’99 (Kyoto, May 1999), many people have requested that the symposium would be held in the capital of Japan and we have agreed. I am very pleased to serve as Conference Chair at a time when high p- formance computing (HPC) has a signi?cant in?uence on computer science and technology. In particular, HPC has had and will continue to have a signi?cant - pact on the advanced technologies of the “IT” revolution. The many conferences and symposiums that are held on the subject around the world are an indication of the importance of this area and the interest of the research community. One of the goals of this symposium is to provide a forum for the discussion of all aspects of HPC (from system architecture to real applications) in a more informal and personal fashion. Today we are delighted to have this symposium, which includes excellent invited talks, tutorials and workshops, as well as high quality technical papers.

Editors and Affiliations

  • Departamento de Arquitectura de Computadores, Universidad Politecnica de Catalunya, Spain

    Mateo Valero

  • Department of Information and Computer Sciences, Nara Women’s University, Japan

    Kazuki Joe

  • Institute of Industrial Science Center for Conceptual Information Processing Research, University of Tokyo, Japan

    Masaru Kitsuregawa

  • Graduate School of Engineering Electrical Engineering Department, University of Tokyo, Japan

    Hidehiko Tanaka

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