Advances in Computer Systems Architecture

1. Front Matter

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2. Keynote Address I

   1. Processor Architecture for Trustworthy Computers

      • Ruby B. Lee

      Pages 1-2

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3. Session 1A: Energy Efficient and Power Aware Techniques

   1. Efficient Voltage Scheduling and Energy-Aware Co-synthesis for Real-Time Embedded Systems

      • Amjad Mohsen, Richard Hofmann

      Pages 3-14

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   2. Energy-Effective Instruction Fetch Unit for Wide Issue Processors

      • Juan L. Aragón, Alexander V. Veidenbaum

      Pages 15-27

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   3. Rule-Based Power-Balanced VLIW Instruction Scheduling with Uncertainty

      • Shu Xiao, Edmund M. -K. Lai, A. B. Premkumar

      Pages 28-40

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   4. An Innovative Instruction Cache for Embedded Processors

      • Cheol Hong Kim, Sung Woo Chung, Chu Shik Jhon

      Pages 41-51

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   5. Dynamic Voltage Scaling for Power Aware Fast Fourier Transform (FFT) Processor

      • David Fitrio, Jugdutt Singh, Aleksandar Stojcevski

      Pages 52-64

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4. Session 1B: Methodologies and Architectures for Application-Specific Systems

   1. Design of an Efficient Multiplier-Less Architecture for Multi-dimensional Convolution

      • Ming Z. Zhang, Hau T. Ngo, Vijayan K. Asari

      Pages 65-78

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   2. A Pipelined Hardware Architecture for Motion Estimation of H.264/AVC

      • Su-Jin Lee, Cheong-Ghil Kim, Shin-Dug Kim

      Pages 79-89

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   3. Embedded Intelligent Imaging On-Board Small Satellites

      • Siti Yuhaniz, Tanya Vladimirova, Martin Sweeting

      Pages 90-103

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   4. Architectural Enhancements for Color Image and Video Processing on Embedded Systems

      • Jongmyon Kim, D. Scott Wills, Linda M. Wills

      Pages 104-117

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   5. A Portable Doppler Device Based on a DSP with High- Performance Spectral Estimation and Output

      • Yufeng Zhang, Yi Zhou, Jianhua Chen, Xinling Shi, Zhenyu Guo

      Pages 118-130

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5. Session 2A: Processor Architectures and Microarchitectures

   1. A Power-Efficient Processor Core for Reactive Embedded Applications

      • Lei Yang, Morteza Biglari-Abhari, Zoran Salcic

      Pages 131-142

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   2. A Stream Architecture Supporting Multiple Stream Execution Models

      • Nan Wu, Mei Wen, Haiyan Li, Li Li, Chunyuan Zhang

      Pages 143-156

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   3. The Challenges of Massive On-Chip Concurrency

      • Kostas Bousias, Chris Jesshope

      Pages 157-170

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   4. FMRPU: Design of Fine-Grain Multi-context Reconfigurable Processing Unit

      • Jih-Ching Chiu, Ren-Bang Lin

      Pages 171-185

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6. Session 2B: High-Reliability and Fault-Tolerant Architectures

   1. Modularized Redundant Parallel Virtual File System

      • Sheng-Kai Hung, Yarsun Hsu

      Pages 186-199

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   2. Resource-Driven Optimizations for Transient-Fault Detecting SuperScalar Microarchitectures

      • Jie S. Hu, G. M. Link, Johnsy K. John, Shuai Wang, Sotirios G. Ziavras

      Pages 200-214

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   3. A Fault-Tolerant Routing Strategy for Fibonacci-Class Cubes

      • Zhang Xinhua, Peter K. K. Loh

      Pages 215-228

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   4. Embedding of Cycles in the Faulty Hypercube

      • Sun-Yuan Hsieh

      Pages 229-235

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On behalf of the ProgramCommittee, we are pleased to present the proceedings of the 2005 Asia-Paci?c Computer Systems Architecture Conference (ACSAC 2005) held in the beautiful and dynamic country of Singapore. This conference was the tenth in its series, one of the leading forums for sharing the emerging research ?ndings in this ?eld. In consultation with the ACSAC Steering Committee, we selected a - member Program Committee. This Program Committee represented a broad spectrum of research expertise to ensure a good balance of research areas, - stitutions and experience while maintaining the high quality of this conference series. This year’s committee was of the same size as last year but had 19 new faces. We received a total of 173 submissions which is 14% more than last year. Each paper was assigned to at least three and in some cases four ProgramC- mittee members for review. Wherever necessary, the committee members called upon the expertise of their colleagues to ensure the highest possible quality in the reviewing process. As a result, we received 415 reviews from the Program Committee members and their 105 co-reviewers whose names are acknowledged inthe proceedings.Theconferencecommitteeadopteda systematicblind review process to provide a fair assessment of all submissions. In the end, we accepted 65 papers on a broad range of topics giving an acceptance rate of 37.5%. We are grateful to all the Program Committee members and the co-reviewers for their e?orts in completing the reviews within a tight schedule.

• Routing
• Scheduling
• Session
• TCP/IP
• algorithms
• caching
• computer architecture
• embedded systems
• high-performance architecture
• image processing
• interconnection networks
• microarchitectures
• network computing
• processor
• reconfigurable architecture

• Centre for High Performance Embedded Systems, School of Computer Engineering, Nanyang Technological University, Singapore

  Thambipillai Srikanthan

• National ICT, Australia

  Jingling Xue

• Centre for High Performance Embedded Systems, Nanyang Technological University, Singapore

  Chip-Hong Chang

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