Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

1. Front Matter

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2. Session 1: Low-Power Processors

   1. A Power-Efficient and Scalable Load-Store Queue Design

      • Fernando Castro, Daniel Chaver, Luis Pinuel, Manuel Prieto, Michael C. Huang, Francisco Tirado

      Pages 1-9

   2. Power Consumption Reduction Using Dynamic Control of Micro Processor Performance

      • David Rios-Arambula, Aurélien Buhrig, Marc Renaudin

      Pages 10-18

   3. Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications

      • Philippe Manet, David Bol, Renaud Ambroise, Jean-Didier Legat

      Pages 19-29

   4. Dynamic Instruction Cascading on GALS Microprocessors

      • Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura

      Pages 30-39

   5. Power Reduction of Superscalar Processor Functional Units by Resizing Adder-Width

      • Guadalupe Miñana, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, José Manuel Colmenar

      Pages 40-48

3. Session 2: Code Optimization for Low-Power

   1. A Retargetable Environment for Power-Aware Code Evaluation: An Approach Based on Coloured Petri Net

      • Meuse N. O. Junior, Paulo Maciel, Ricardo Lima, Angelo Ribeiro, Cesar Oliveira, Adilson Arcoverde et al.

      Pages 49-58

   2. Designing Low-Power Embedded Software for Mass-Produced Microprocessor by Using a Loop Table in On-Chip Memory

      • Rodrigo Possamai Bastos, Fernanda Lima Kastensmidt, Ricardo Reis

      Pages 59-68

   3. Energy Characterization of Garbage Collectors for Dynamic Applications on Embedded Systems

      • Jose M. Velasco, David Atienza, Katzalin Olcoz, Francky Catthoor, Francisco Tirado, J. M. Mendias

      Pages 69-78

   4. Optimizing the Configuration of Dynamic Voltage Scaling Points in Real-Time Applications

      • Huizhan Yi, Xuejun Yang

      Pages 79-88

4. Session 3: High-Level Design

   1. Systematic Preprocessing of Data Dependent Constructs for Embedded Systems

      • Martin Palkovic, Erik Brockmeyer, P. Vanbroekhoven, Henk Corporaal, Francky Catthoor

      Pages 89-98

   2. Temperature Aware Datapath Scheduling

      • Ali Manzak

      Pages 99-106

   3. Memory Hierarchy Energy Cost of a Direct Filtering Implementation of the Wavelet Transform

      • Bert Geelen, Gauthier Lafruit, V. Ferentinos, R. Lauwereins, Diederik Verkest

      Pages 107-116

   4. Improving the Memory Bandwidth Utilization Using Loop Transformations

      • Minas Dasygenis, Erik Brockmeyer, Francky Catthoor, Dimitrios Soudris, Antonios Thanailakis

      Pages 117-126

   5. Power-Aware Scheduling for Hard Real-Time Embedded Systems Using Voltage-Scaling Enabled Architectures

      • Amjad Mohsen, Richard Hofmann

      Pages 127-136

5. Session 4: Telecommunications and Signal Processing

   1. Design of Digital Filters for Low Power Applications Using Integer Quadratic Programming

      • Mustafa Aktan, Günhan Dündar

      Pages 137-145

   2. A High Level Constant Coefficient Multiplier Power Model for Power Estimation on High Levels of Abstraction

      • Arne Schulz, Andreas Schallenberg, Domenik Helms, Milan Schulte, Axel Reimer, Wolfgang Nebel

      Pages 146-155

   3. An Energy-Tree Based Routing Algorithm in Wireless Ad-Hoc Network Environments

      • Hyun Ho Kim, Jung Hee Kim, Yong-hyeog Kang, Young Ik Eom

      Pages 156-165

   4. Energy-Aware System-on-Chip for 5 GHz Wireless LANs

      • Labros Bisdounis, Spyros Blionas, Enrico Macii, Spiridon Nikolaidis, Roberto Zafalon

      Pages 166-176

   5. Low-Power VLSI Architectures for OFDM Transmitters Based on PAPR Reduction

      • Th. Giannopoulos, Vassilis Paliouras

      Pages 177-186

Welcome to the proceedings of PATMOS 2005, the 15th in a series of international workshops.PATMOS2005wasorganizedbyIMECwithtechnicalco-sponsorshipfrom the IEEE Circuits and Systems Society. Over the years, PATMOS has evolved into an important European event, where - searchers from both industry and academia discuss and investigate the emerging ch- lenges in future and contemporary applications, design methodologies, and tools - quired for the developmentof upcominggenerationsof integrated circuits and systems. The technical program of PATMOS 2005 contained state-of-the-art technical contri- tions, three invited talks, a special session on hearing-aid design, and an embedded - torial. The technical program focused on timing, performance and power consumption, as well as architectural aspects with particular emphasis on modeling, design, char- terization, analysis and optimization in the nanometer era. The Technical Program Committee, with the assistance of additional expert revi- ers, selected the 74 papers to be presented at PATMOS. The papers were divided into 11 technical sessions and 3 poster sessions. As is always the case with the PATMOS workshops, the review process was anonymous, full papers were required, and several reviews were carried out per paper. Beyond the presentations of the papers, the PATMOS technical program was - riched by a series of speeches offered by world class experts, on important emerging research issues of industrial relevance. Prof. Jan Rabaey, Berkeley, USA, gave a talk on “Traveling the Wild Frontier of Ulta Low-Power Design”, Dr. Sung Bae Park, S- sung, gave a presentation on “DVL (Deep Low Voltage): Circuits and Devices”, Prof.

• Automat
• automation
• communication
• integrated circuit
• modeling
• optimization
• processor
• simulation
• system on chip (SoC)
• telecommunications

• Electrical and Computer Engineering Department, University of Patras, Greece

  Vassilis Paliouras

• IMEC, Heverlee, Belgium

  Johan Vounckx

• Dept. of Electrical Engineering, VUB, Brussels, Belgium

  Diederik Verkest

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