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Power-Aware Computer Systems

4th International Workshop, PACS 2004, Portland, OR, USA, December 5, 2004, Revised Selected Papers

  • Conference proceedings
  • © 2005

Overview

Editors:
  1. Babak Falsafi

    1. Electrical and Computer Engineering, Computer Science, Carnegie Mellon University, Pittsburgh, USA

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    You can also search for this editor in PubMed   Google Scholar

  2. T. N. VijayKumar

    1. ECE, Purdue University, USA

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    You can also search for this editor in PubMed   Google Scholar

Part of the book series: Lecture Notes in Computer Science (LNCS, volume 3471)

Part of the book sub series: Theoretical Computer Science and General Issues (LNTCS)

Included in the following conference series:

Conference proceedings info: PACS 2004.

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Table of contents (13 papers)

  1. Front Matter

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  2. Microarchitecture- and Circuit-Level Techniques

    1. An Optimized Front-End Physical Register File with Banking and Writeback Filtering

      • Miquel Pericàs, Ruben Gonzalez, Adrian Cristal, Alex Veidenbaum, Mateo Valero
      Pages 1-14

    2. Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization

      • Joseph Sharkey, Dmitry Ponomarev, Kanad Ghose, Oguz Ergin
      Pages 15-29

    3. Bit-Sliced Datapath for Energy-Efficient High Performance Microprocessors

      • Sumeet Kumar, Prateek Pujara, Aneesh Aggarwal
      Pages 30-45

    4. Low-Overhead Core Swapping for Thermal Management

      • Eren Kursun, Glenn Reinman, Suleyman Sair, Anahita Shayesteh, Tim Sherwood
      Pages 46-60

  3. Power-Aware Memory and Interconnect Systems

    1. Software–Hardware Cooperative Power Management for Main Memory

      • H. Huang, K. G. Shin, C. Lefurgy, K. Rajamani, T. Keller, E. Hensbergen et al.
      Pages 61-77

    2. Energy-Aware Data Prefetching for General-Purpose Programs

      • Yao Guo, Saurabh Chheda, Israel Koren, C. Mani Krishna, Csaba Andras Moritz
      Pages 78-94

    3. Bus Power Estimation and Power-Efficient Bus Arbitration for System-on-a-Chip Embedded Systems

      • Ke Ning, David Kaeli
      Pages 95-106

    4. Context-Independent Codes for Off-Chip Interconnects

      • Kartik Mohanram, Scott Rixner
      Pages 107-119

  4. Frequency-/Voltage-Scaling Techniques

    1. Dynamic Processor Throttling for Power Efficient Computations

      • Masaaki Kondo, Hiroshi Nakamura
      Pages 120-134

    2. Effective Dynamic Voltage Scaling Through CPU-Boundedness Detection

      • Chung-Hsing Hsu, Wu-Chun Feng
      Pages 135-149

    3. Safe Overprovisioning: Using Power Limits to Increase Aggregate Throughput

      • Mark E. Femal, Vincent W. Freeh
      Pages 150-164

    4. Power Consumption Breakdown on a Modern Laptop

      • Aqeel Mahesri, Vibhore Vardhan
      Pages 165-180

  5. Erratum

    1. Erratum

      • Editorial Board
      Pages E1-E1

  6. Back Matter

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  1. Power-Aware Computer Systems

Keywords

About this book

Welcome to the proceedings of the Power-Aware Computer Systems (PACS 2004) workshop held in conjunction with the 37th Annual International Sym- sium on Microarchitecture (MICRO-37). The continued increase of power and energy dissipation in computer systems has resulted in higher cost, lower re- ability, and reduced battery life in portable systems. Consequently, power and energy have become ?rst-class constraints at all layers of modern computer s- tems. PACS 2004 is the fourth workshop in its series to explore techniques to reduce power and energy at all levels of computer systems and brings together academic and industry researchers. The papers in these proceedings span a wide spectrum of areas in pow- aware systems. We have grouped the papers into the following categories: (1) microarchitecture- and circuit-level techniques, (2) power-aware memory and interconnect systems, and (3) frequency- and voltage-scaling techniques. The ?rst paper in the microarchitecture group proposes banking and wri- back ?ltering to reduce register ?le power. The second paper in this group - timizes both delay and power of the issue queue by packing two instructions in each issue queue entry and by memorizing upper-order bits of the wake-up tag. The third paper proposes bit slicing the datapath to exploit narrow width operations, and the last paper proposes to migrate application threads from one core to another in a multi-core chip to address thermal problems.

Editors and Affiliations

  • Electrical and Computer Engineering, Computer Science, Carnegie Mellon University, Pittsburgh, USA

    Babak Falsafi

  • ECE, Purdue University, USA

    T. N. VijayKumar

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