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Advances in Computer Systems Architecture

9th Asia-Pacific Conference, ACSAC 2004, Beijing, China, September 7-9, 2004, Proceedings

  • Conference proceedings
  • © 2004

Overview

Editors:
  1. Pen-Chung Yew

    1. Department of Computer Science, University of Minnesota, Minneapolis

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  2. Jingling Xue

    1. National ICT, Australia

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Part of the book series: Lecture Notes in Computer Science (LNCS, volume 3189)

Included in the following conference series:

Conference proceedings info: ACSAC 2004.

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Table of contents (48 papers)

  1. Front Matter

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  2. Keynote Address I

    1. Some Real Observations on Virtual Machines

      • James E. Smith
      Pages 1-1

  3. Session 1A: Cache and Memory

    1. Replica Victim Caching to Improve Reliability of In-Cache Replication

      • Wei Zhang
      Pages 2-15

    2. Efficient Victim Mechanism on Sector Cache Organization

      • Chunrong Lai, Shih-Lien Lu
      Pages 16-29

    3. Cache Behavior Analysis of a Compiler-Assisted Cache Replacement Policy

      • Xingyan Tian, Kejia Zhao, Huowang Chen, Hongyan Du
      Pages 30-43

    4. Modeling the Cache Behavior of Codes with Arbitrary Data-Dependent Conditional Structures

      • Diego Andrade, Basilio B. Fraguela, Ramón Doallo
      Pages 44-57

  4. Session 1B: Reconfigurable and Embedded Architectures

    1. A Configurable System-on-Chip Architecture for Embedded Devices

      • Sebastian Wallner
      Pages 58-71

    2. An Auto-adaptative Reconfigurable Architecture for the Control

      • Nicolas Ventroux, Stéphane Chevobbe, Fréderic Blanc, Thierry Collette
      Pages 72-87

    3. Enhancing the Memory Performance of Embedded Systems with the Flexible Sequential and Random Access Memory

      • Ying Chen, Karthik Ranganathan, Vasudev V. Pai, David J. Lilja, Kia Bazargan
      Pages 88-101

    4. Heuristic Algorithm for Reducing Mapping Sets of Hardware-Software Partitioning in Reconfigurable System

      • Seong-Yong Ahn, Jun-Yong Kim, Jeong-A Lee
      Pages 102-114

  5. Session 2A: Processor Architecture and Design I

    1. Architecture Design of a High-Performance 32-Bit Fixed-Point DSP

      • Jian Chen, Ruhao Xu, Yuzhuo Fu
      Pages 115-125

    2. TengYue-1: A High Performance Embedded SoC

      • Lei Wang, Hong-yi Lu, Kui Dai, Zhi-ying Wang
      Pages 126-136

    3. A Fault-Tolerant Single-Chip Multiprocessor

      • Wenbin Yao, Dongsheng Wang, Weimin Zheng
      Pages 137-145

  7. Session 3A: Processor Architecture and Design II

    1. Dynamic Reallocation of Functional Units in Superscalar Processors

      • Marc Epalza, Paolo Ienne, Daniel Mlynek
      Pages 185-198

    2. Multiple-Dimension Scalable Adaptive Stream Architecture

      • Mei Wen, Nan Wu, Haiyan Li, Chunyuan Zhang
      Pages 199-211

    3. Impact of Register-Cache Bandwidth Variation on Processor Performance

      • Kentaro Hamayasu, Vasily G. Moshnyaga
      Pages 212-225

  8. Session 3B: Compiler and Operating System Issues

    1. Exploiting Free Execution Slots on EPIC Processors for Efficient and Accurate Runtime Profiling

      • Youfeng Wu, Yong-Fong Lee
      Pages 226-240
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  1. Advances in Computer Systems Architecture

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About this book

On behalf of the program committee, we were pleased to present this year’s program for ACSAC: Asia-Paci?c Computer Systems Architecture Conference. Now in its ninth year, ACSAC continues to provide an excellent forum for researchers, educators and practitioners to come to the Asia-Paci?c region to exchange ideas on the latest developments in computer systems architecture. This year, the paper submission and review processes were semiautomated using the free version of CyberChair. We received 152 submissions, the largest number ever.Eachpaperwasassignedatleastthree,mostlyfour,andinafewcaseseven ?ve committee members for review. All of the papers were reviewed in a t- monthperiod,duringwhichtheprogramchairsregularlymonitoredtheprogress of the review process. When reviewers claimed inadequate expertise, additional reviewers were solicited. In the end, we received a total of 594 reviews (3.9 per paper) from committee members as well as 248 coreviewers whose names are acknowledged in the proceedings. We would like to thank all of them for their time and e?ort in providing us with such timely and high-quality reviews, some of them on extremely short notice.

Editors and Affiliations

  • Department of Computer Science, University of Minnesota, Minneapolis

    Pen-Chung Yew

  • National ICT, Australia

    Jingling Xue

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