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Power-Aware Computer Systems

Third International Workshop, PACS 2003, San Diego, CA, USA, December 1, 2003, Revised Papers

  • Conference proceedings
  • © 2005

Overview

Editors:
  1. Babak Falsafi

    1. Electrical and Computer Engineering, Computer Science, Carnegie Mellon University, Pittsburgh, USA

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    You can also search for this editor in PubMed   Google Scholar

  2. T. N. VijayKumar

    1. ECE, Purdue University, USA

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    You can also search for this editor in PubMed   Google Scholar

Part of the book series: Lecture Notes in Computer Science (LNCS, volume 3164)

Included in the following conference series:

Conference proceedings info: PACS 2003.

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Table of contents (14 papers)

  1. Front Matter

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  2. Compilers

    1. Runtime Biased Pointer Reuse Analysis and Its Application to Energy Efficiency

      • Yao Guo, Saurabh Chheda, Csaba Andras Moritz
      Pages 1-12

    2. Inter-program Compilation for Disk Energy Reduction

      • Jerry Hom, Ulrich Kremer
      Pages 13-25

  3. Embedded Systems

    1. Energy Consumption in Mobile Devices: Why Future Systems Need Requirements–Aware Energy Scale-Down

      • Robert N. Mayo, Parthasarathy Ranganathan
      Pages 26-40

    2. Efficient Scratchpad Allocation Algorithms for Energy Constrained Embedded Systems

      • Manish Verma, Lars Wehmeyer, Peter Marwedel
      Pages 41-56

    3. Online Prediction of Battery Lifetime for Embedded and Mobile Devices

      • Ye Wen, Rich Wolski, Chandra Krintz
      Pages 57-72

    4. Synchroscalar: Initial Lessons in Power-Aware Design of a Tile-Based Embedded Architecture

      • John Oliver, Ravishankar Rao, Paul Sultana, Jedidiah Crandall, Erik Czernikowski, Leslie W. Jones IV et al.
      Pages 73-85

    5. Heterogeneous Wireless Network Management

      • Wajahat Qadeer, Tajana Simunic Rosing, John Ankcorn, Venky Krishnan, Givanni De Micheli
      Pages 86-100

  4. Microarchitectural Techniques

    1. “Look It Up” or “Do the Math”: An Energy, Area, and Timing Analysis of Instruction Reuse and Memoization

      • Daniel Citron, Dror G. Feitelson
      Pages 101-116

    2. CPU Packing for Multiprocessor Power Reduction

      • Soraya Ghiasi, Wes Felter
      Pages 117-131

    3. Exploring the Potential of Architecture-Level Power Optimizations

      • John S. Seng, Dean M. Tullsen
      Pages 132-147

    4. Coupled Power and Thermal Simulation with Active Cooling

      • Weiping Liao, Lei He
      Pages 148-163

  5. Cache and Memory Systems

    1. The Synergy Between Power-Aware Memory Systems and Processor Voltage Scaling

      • Xiaobo Fan, Carla S. Ellis, Alvin R. Lebeck
      Pages 164-179

    2. Hot-and-Cold: Using Criticality in the Design of Energy-Efficient Caches

      • Rajeev Balasubramonian, Viji Srinivasan, Sandhya Dwarkadas, Alper Buyuktosunoglu
      Pages 180-195

    3. PARROT: Power Awareness Through Selective Dynamically Optimized Traces

      • Roni Rosner, Yoav Almog, Micha Moffie, Naftali Schwartz, Avi Mendelson
      Pages 196-214

  6. Back Matter

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  1. Power-Aware Computer Systems

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About this book

Welcome to the proceedings of the 3rd Power-Aware Computer Systems (PACS 2003) Workshop held in conjunction with the 36th Annual International Symposium on Microarchitecture (MICRO-36). The increase in power and - ergy dissipation in computer systems has begun to limit performance and has also resulted in higher cost and lower reliability. The increase also implies - ducedbatterylifeinportablesystems.Becauseofthemagnitudeoftheproblem, alllevelsofcomputersystems,includingcircuits,architectures,andsoftware,are being employed to address power and energy issues. PACS 2003 was the third workshop in its series to explore power- and energy-awareness at all levels of computer systems and brought together experts from academia and industry. These proceedings include 14 research papers, selected from 43 submissions, spanningawidespectrumofareasinpower-awaresystems.Wehavegrouped the papers into the following categories: (1) compilers, (2) embedded systems, (3) microarchitectures, and (4) cache and memory systems. The ?rst paper on compiler techniques proposes pointer reuse analysis that is biased by runtime information (i.e., the targets of pointers are determined based on the likelihood of their occurrence at runtime) to map accesses to ener- e?cient memory access paths (e.g., avoid tag match). Another paper proposes compiling multiple programs together so that disk accesses across the programs can be synchronized to achieve longer sleep times in disks than if the programs are optimized separately.

Editors and Affiliations

  • Electrical and Computer Engineering, Computer Science, Carnegie Mellon University, Pittsburgh, USA

    Babak Falsafi

  • ECE, Purdue University, USA

    T. N. VijayKumar

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