Higher-Level Hardware Synthesis

1. Front Matter

   PDF

2. 1. Introduction

   1. 1. Introduction

      • Richard Sharp

      Pages 1-18

   2. 2. Related Work

      • Richard Sharp

      Pages 19-34

   3. 3. The SAFL Language

      • Richard Sharp

      Pages 35-50

   4. 4. Soft Scheduling

      • Richard Sharp

      Pages 51-64

   5. 5. High-Level Synthesis of SAFL

      • Richard Sharp

      Pages 65-86

   6. 6. Analysis and Optimisation of Intermediate Code

      • Richard Sharp

      Pages 87-111

   7. 7. Dealing with I/O

      • Richard Sharp

      Pages 113-127

   8. 8. Combining Behaviour and Structure

      • Richard Sharp

      Pages 129-139

   9. 9. Transformation of SAFL Specifications

      • Richard Sharp

      Pages 141-154

   10. 10. Case Study

       • Richard Sharp

       Pages 155-168

   11. 11. Conclusions and Further Work

       • Richard Sharp

       Pages 169-170

3. Appendix

   1. Appendix

      • Richard Sharp

      Pages 171-182

4. Back Matter

   PDF

In the mid 1960s, when a single chip contained an average of 50 transistors, Gordon Moore observed that integrated circuits were doubling in complexity every year. In an in?uential article published by Electronics Magazine in 1965, Moore predicted that this trend would continue for the next 10 years. Despite being criticized for its “unrealistic optimism,” Moore’s prediction has remained valid for far longer than even he imagined: today, chips built using state-- the-art techniques typically contain several million transistors. The advances in fabrication technology that have supported Moore’s law for four decades have fuelled the computer revolution. However,this exponential increase in transistor density poses new design challenges to engineers and computer scientists alike. New techniques for managing complexity must be developed if circuits are to take full advantage of the vast numbers of transistors available. In this monograph we investigate both (i) the design of high-level languages for hardware description, and (ii) techniques involved in translating these hi- level languages to silicon. We propose SAFL, a ?rst-order functional language designedspeci?callyforbehavioralhardwaredescription,anddescribetheimp- mentation of its associated silicon compiler. We show that the high-level pr- erties of SAFL allow one to exploit program analyses and optimizations that are not employed in existing synthesis systems. Furthermore, since SAFL fully abstracts the low-leveldetails of the implementation technology, we show how it can be compiled to a range of di?erent design styles including fully synchronous design and globally asynchronous locally synchronous (GALS) circuits.

• Hardware
• SAFL
• VHDL
• VLSI specifications
• Verilog
• compiler
• complexity
• functional languages
• hardware description languages
• hardware design
• hardware synthesis
• hardware/software codesign
• systems design
• systems optimization
• systems specification

• Intel Research, Cambridge, UK

  Richard Sharp

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