Third Caltech Conference on Very Large Scale Integration

1. Front Matter

   Pages i-xii

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2. Invited Papers

   1. Front Matter

      Pages xiii-xiii

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   2. Practical Experience With VLSI Methodology

      • Egon Hörbst, Gerd Sandweg, Stefan Wallstab

      Pages 1-13

   3. CAPRI: A Design Methodology and a Silicon Compiler for VLSI Circuits Specified by Algorithms

      • F. Anceau

      Pages 15-31

   4. Design of a High Performance VLSI Processor

      • John L. Hennessy, Norman P. Jouppi, Steven Przybylski, Christopher Rowen, Thomas Gross

      Pages 33-54

   5. Fundamental Issues in the Electrical Design of VLSI Circuits

      • Daniel W. Dobberpuhl

      Pages 55-55

3. Circuit Timing

   1. Front Matter

      Pages N3-N3

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   2. Crystal: A Timing Analyzer for nMOS VLSI Circuits

      • John K. Ousterhout

      Pages 57-69

   3. TV: An nMOS Timing Analyzer

      • Norman P. Jouppi

      Pages 71-85

   4. Optimizing Synchronous Circuitry by Retiming (Preliminary Version)

      • Charles E. Leiserson, Flavio M. Rose, James B. Saxe

      Pages 87-116

4. Routing and Interconnection

   1. Front Matter

      Pages N5-N5

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   2. A New Channel Routing Algorithm

      • Wan S. Chan

      Pages 117-139

   3. River Routing: Methodology and Analysis

      • Ron Y. Pinter

      Pages 141-163

   4. Area and Delay Penalties in Restructurable Wafer-Scale Arrays

      • Jonathan W. Greene, Abbas EI Gamal

      Pages 165-184

5. Formal System Models

   1. Front Matter

      Pages N7-N7

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   2. Verification of VLSI Designs

      • Robert E. Shostak

      Pages 185-206

   3. A Hierarchical Simulator Based on Formal Semantics

      • Marina C. Chen, Carver A. Mead

      Pages 207-223

   4. Trace Theory and the Definition of Hierarchical Components

      • Martin Rem, Jan L. A. van de Snepscheut, Jan Tijmen Udding

      Pages 225-239

   5. Deriving Circuits from Programs

      • Jan L. A. van de Snepscheut

      Pages 241-256

6. System Building Blocks

   1. Front Matter

      Pages N9-N9

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The papers in this book were presented at the Third Caltech Conference on Very Large Scale Integration, held March 21-23, 1983 in Pasadena, California. The conference was organized by the Computer Science Depart­ ment, California Institute of Technology, and was partly supported by the Caltech Silicon Structures Project. This conference focused on the role of systematic methodologies, theoretical models, and algorithms in all phases of the design, verification, and testing of very large scale integrated circuits. The need for such disciplines has arisen as a result of the rapid progress of integrated circuit technology over the past 10 years. This progress has been driven largely by the fabrica­ tion technology, providing the capability to manufacture very complex elec­ tronic systems reliably and at low cost. At this point the capability to manufac­ ture very large scale integrated circuits has exceeded our capability to develop new product designs quickly, reliably, and at a reasonable cost. As a result new designs are undertaken only if the production volume will be large enough to amortize high design costs, products first appear on the market well past their announced delivery date, and reference manuals must be amended to document design flaws. Recent research in universities and in private industry has created an emerg­ ing science of very large scale integration.

• Integrierte Schaltung
• Schaltung
• VLSI
• integrated circuit
• production

• California Institute of Technology, USA

  Randal Bryant

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