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Concurrency and Hardware Design

Advances in Petri Nets

  • Book
  • © 2002

Overview

Editors:
  1. Jordi Cortadella

    1. Department of Software, Technical University of Catalonia, Barcelona, Spain

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    You can also search for this editor in PubMed   Google Scholar

  2. Alex Yakovlev

    1. School of Electrical, Electronic and Computer Engineering, University of Newcastle, UK

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    You can also search for this editor in PubMed   Google Scholar

  3. Grzegorz Rozenberg

    1. Center for Natural Computing, Leiden University, Leiden, The Netherlands

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    You can also search for this editor in PubMed   Google Scholar

Part of the book series: Lecture Notes in Computer Science (LNCS, volume 2549)

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Table of contents (9 chapters)

  1. Front Matter

    Pages I-X
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  2. Formal Models

    1. Composing Snippets

      • Igor Benko, Jo Ebergen
      Pages 1-33

    2. A Programming Approach to the Design of Asynchronous Logic Blocks

      • Mark B. Josephs, Dennis P. Furey
      Pages 34-60

  3. Asynchronous Circuits

    1. GALA (Globally Asynchronous — Locally Arbitrary) Design

      • Victor Varshavsky, Vyacheslav Marakhovsky
      Pages 61-107

    2. Synthesis of Reactive Systems: Application to Asynchronous Circuit Design

      • Josep Carmona, Jordi Cortadella, Enric Pastor
      Pages 108-151

    3. Decomposition in Asynchronous Circuit Design

      • Walter Vogler, Ralf Wollowski
      Pages 152-190

  4. Embedded System Design

    1. Functional and Performance Modeling of Concurrency in VCC

      • William LaRue, Sherry Solden, Bishnupriya Bhattacharya
      Pages 191-227

    2. Modeling and Designing Heterogeneous Systems

      • Felice Balarin, Luciano Lavagno, Claudio Passerone, Alberto Sangiovanni-Vincentelli, Marco Sgroi, Yosinori Watanabe
      Pages 228-273

  5. Timed Verification and Performance Analysis

    1. Timed Verification of Asynchronous Circuits

      • Jesper Møller, Henrik Hulgaard, Henrik Reif Andersen
      Pages 274-312

    2. Performance Analysis of Asynchronous Circuits Using Markov Chains

      • Peter A. Beerel, Aiguo Xie
      Pages 313-343

  6. Back Matter

    Pages 345-345
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Keywords

About this book

As CMOS semiconductor technology strides towards billions of transistors on a single die new problems arise on the way. They are concerned with the - minishing fabrication process features, which a?ect for example the gate-to-wire delay ratio. They manifest themselves in greater variations of size and operating parameters of devices, which put the overall reliability of systems at risk. And, most of all, they have tremendous impact on design productivity, where the costs of utilizing the growing silicon ‘real estate’ rocket to billions of dollars that have to be spent on design, veri?cation, and testing. All such problems call for new - sign approaches and models for digital systems. Furthermore, new developments in non-CMOS technologies, such as single-electron transistors, rapid single-?- quantum devices, quantum dot cells, molecular devices, etc. , add extra demand for new research in system design methodologies. What kind of models and design methodologies will be required to build systems in all these new technologies? Answering this question, even for each particular type of new technology generation, is not easy, especially because sometimes it is not even clear what kind of elementary devices are feasible there. This problem is of an interdisciplinary nature. It requires an bridges between di?erent scienti?c communities. The bridges must be built very quickly, and be maximally ?exible to accommodate changes taking place in a logarithmic timescale.

Editors and Affiliations

  • Department of Software, Technical University of Catalonia, Barcelona, Spain

    Jordi Cortadella

  • School of Electrical, Electronic and Computer Engineering, University of Newcastle, UK

    Alex Yakovlev

  • Center for Natural Computing, Leiden University, Leiden, The Netherlands

    Grzegorz Rozenberg

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