Overview
- Provides the first book related exclusively to the problem of multi-cell fault detection by multi-run tests in memory testing process
- Presents practical algorithms for design and implementation of efficient multi-run tests
- Demonstrates methods verified by analytical and experimental investigations
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Table of contents (8 chapters)
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Front Matter
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Back Matter
Keywords
About this book
This book describes efficient techniques for production testing as well as for periodic maintenance testing (specifically in terms of multi-cell faults) in modern semiconductor memory. The author discusses background selection and address reordering algorithms in multi-run transparent march testing processes. Formal methods for multi-run test generation and many solutions to increase their efficiency are described in detail. All methods presented ideas are verified by both analytical investigations and numerical simulations.
- Provides the first book related exclusively to the problem of multi-cell fault detection by multi-run tests in memory testing process;
- Presents practical algorithms for design and implementation of efficient multi-run tests;
- Demonstrates methods verified by analytical and experimental investigations.
Authors and Affiliations
About the author
Ireneusz Mrozek received his M.Sc. and Ph.D. degrees in computer science in 1994 and 2004,respectively. Since 1994 he has been employed at the Faculty of Computer Science of Bialystok Technical University (Poland). His main research interests include the area of diagnostic testing of embedded memories. Particularly, he focuses on transparent tests for RAM as well as the application of these in the BIST or BISR schemes. He has also gained industrial experience working as a Senior Software Engineer at Motorola Solutions.
Bibliographic Information
Book Title: Multi-run Memory Tests for Pattern Sensitive Faults
Authors: Ireneusz Mrozek
DOI: https://doi.org/10.1007/978-3-319-91204-2
Publisher: Springer Cham
eBook Packages: Engineering, Engineering (R0)
Copyright Information: Springer International Publishing AG, part of Springer Nature 2019
Hardcover ISBN: 978-3-319-91203-5Published: 18 July 2018
Softcover ISBN: 978-3-030-08198-0Published: 01 February 2019
eBook ISBN: 978-3-319-91204-2Published: 06 July 2018
Edition Number: 1
Number of Pages: X, 135
Number of Illustrations: 34 b/w illustrations
Topics: Circuits and Systems, Processor Architectures, Electronics and Microelectronics, Instrumentation