Overview
- Describes in detail the digital design of integrated circuit under process variations with a focus on design-time understanding and optimization
- Follows a step-by-step sequence in methodology, going from logic gates to logic paths to circuit level, in order to explain the behavior of process variations at the different levels of abstraction
- Presents novel design issues for FinFET based digital circuits
- Provides step-by-step examples of quantitative estimation of the timing performance of logic cells and logic paths, as well as a comparison with Spice simulation results
Part of the book series: Frontiers in Electronic Testing (FRET, volume 39)
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Table of contents (7 chapters)
Keywords
About this book
Authors and Affiliations
About the authors
Victor Champac received the Electrical Engineering Degree in 1987 from the Autonomous University of Nuevo Leon, Mexico. He received the Ph.D. degree in 1993 from the Polytechnic University of Catalonia (UPC), Spain. From 1988 to 1993 he was Associate Professor at the Electronic Engineering Department of the UPC. In 1993 he joined the National Institute for Astrophysics, Optics and Electronics (INAOE) in Mexico where he is Titular Professor. He made sabbatical in 2001-2002 at Motorola and in 2010-2011 at the University of California (UCSD). Dr. Champac was a co-founder of the Test Technology Technical Council-Latin America of IEEE Computer Society. He was co-General Chair of the 2nd, 9th, 13th and 16th IEEE Latin-American Test Workshop (now Latin-American Test Symposium). He has also served as Guest Editor of the Journal of Electronics Testing, Springer. He is member of the Editorial Board of Journal of Electronic Testing (JETTA). He is a Senior member of the IEEE and the National Research System (SNI) in Mexico. He has served as program and organizing committee member of several international conferences. Dr. Champac received the best paper award of the IEEE Latin American Test Workshop in 2008. He has published more than 120 papers in international journals and conferences. His research lines include: circuit design under process variations, aging reliable circuit design, defect modeling in leading technologies, and development of new test strategies.
Jose Garcia Gervacio received the Electronics Engineering Degree in 1987 from the Technological Institute of Celaya, Mexico. He received the Master and Ph.D. degree in 2003 and 2009, respectively, from the National Institute for Astrophysics, Optics, and Electronics (INAOE), Mexico. From 2010 to 2011 he was an assistant professor at INAOE. From 2011 to 2013 he occupied a postdoctoral position in the Research center in Micro and Nanotechnology (MICRONA) of the University Veracruzana. Since 2013 he is Full-time Professor of the University Veracruzana in Xalapa, Mexico. He has served as program and organizing committee member of the 4th Biannual European - Latin American Summer School on Design, Test, and Reliability (BELAS-2015). He served as organizing committee member of the 16th IEEE Latin American Test Symposium (LATS-2015). His research interest is focused on the design and testing of VLSI digital circuits.
Bibliographic Information
Book Title: Timing Performance of Nanometer Digital Circuits Under Process Variations
Authors: Victor Champac, Jose Garcia Gervacio
Series Title: Frontiers in Electronic Testing
DOI: https://doi.org/10.1007/978-3-319-75465-9
Publisher: Springer Cham
eBook Packages: Engineering, Engineering (R0)
Copyright Information: Springer International Publishing AG, part of Springer Nature 2018
Hardcover ISBN: 978-3-319-75464-2Published: 27 April 2018
Softcover ISBN: 978-3-030-09239-9Published: 12 January 2019
eBook ISBN: 978-3-319-75465-9Published: 18 April 2018
Series ISSN: 0929-1296
Edition Number: 1
Number of Pages: XVIII, 185
Number of Illustrations: 25 b/w illustrations, 91 illustrations in colour
Topics: Circuits and Systems, Processor Architectures, Electronics and Microelectronics, Instrumentation