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Soft Error Mechanisms, Modeling and Mitigation

  • Book
  • © 2016

Overview

Authors:
  1. Selahattin Sayil

    1. Houston, USA

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  • Introduces readers to various radiation soft-error mechanisms such as soft delays, radiation induced jitter and race, single event coupling noise, delay and speed-up effects and then compares coupling induced noise and delay effects to single event transients and soft delays
  • Presents closed form expressions for single event crosstalk noise, delay and speed-up effects
  • Includes a reliability analysis of low power energy-efficient designs so that reader can make clever design choices that reduce static power consumption and improve soft error reliability

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Table of contents (9 chapters)

  1. Front Matter

    Pages i-xi
    Download chapter PDF

  2. Introduction

    • Selahattin Sayil
    Pages 1-10

  3. Mitigation of Single Event Effects

    • Selahattin Sayil
    Pages 11-18

  4. Transmission Gate (TG) Based Soft Error Mitigation Methods

    • Selahattin Sayil
    Pages 19-30

  5. Single Event Soft Error Mechanisms

    • Selahattin Sayil
    Pages 31-48

  6. Modeling Single Event Crosstalk Noise in Nanometer Technologies

    • Selahattin Sayil
    Pages 49-62

  7. Modeling of Single Event Coupling Delay and Speedup Effects

    • Selahattin Sayil
    Pages 63-74

  8. Single Event Upset Hardening of Interconnects

    • Selahattin Sayil
    Pages 75-84

  9. Soft-Error Aware Power Optimization

    • Selahattin Sayil
    Pages 85-93

  10. Dynamic Threshold Technique for Soft Error and Soft Delay Mitigation

    • Selahattin Sayil
    Pages 95-103

  11. Back Matter

    Pages 105-105
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Keywords

About this book

This book introduces readers to various radiation soft-error mechanisms such as soft delays, radiation induced clock jitter and pulses, and single event (SE) coupling induced effects. In addition to discussing various radiation hardening techniques for combinational logic, the author also describes new mitigation strategies targeting commercial designs. Coverage includes novel soft error mitigation techniques such as the Dynamic Threshold Technique and Soft Error Filtering based on Transmission gate with varied gate and body bias. The discussion also includes modeling of SE crosstalk noise, delay and speed-up effects. Various mitigation strategies to eliminate SE coupling effects are also introduced. Coverage also includes the reliability of low power energy-efficient designs and the impact of leakage power consumption optimizations on soft error robustness. The author presents an analysis of various power optimization techniques, enabling readers to make design choices that reduce static power consumption and improve soft error reliability at the same time.  

Reviews

“Book gives wide perspectives on the technical insights of fundamentals of sources and mitigation strategies of soft error rates in semiconductor memory devices … . a valuable addition to a scientific library, as well as served as good introduction for memory reliability engineers or specialists and   industrials involved in the field of memory device reliability. This book is highly recommended for people who desire a better understanding of the theory and practice of SER and technical considerations in SER mitigations.” (Chong Leong Gan, Microelectronics Reliability, Vol. 74 (81), 2017)

Authors and Affiliations

  • Houston, USA

    Selahattin Sayil

About the author

Dr. Selahattin Sayil is an Associate Professor in the Philip M. Drayer Department of Electrical Engineering at Lamar University.  His research focuses on Radiation effects modeling and hardening at the circuit level, Reliability analysis of low power designs, and Interconnect modeling and noise prediction.

Bibliographic Information

  • Book Title: Soft Error Mechanisms, Modeling and Mitigation

  • Authors: Selahattin Sayil

  • DOI: https://doi.org/10.1007/978-3-319-30607-0

  • Publisher: Springer Cham

  • eBook Packages: Engineering, Engineering (R0)

  • Copyright Information: Springer International Publishing Switzerland 2016

  • Hardcover ISBN: 978-3-319-30606-3Published: 04 March 2016

  • Softcover ISBN: 978-3-319-80848-2Published: 15 June 2018

  • eBook ISBN: 978-3-319-30607-0Published: 25 February 2016

  • Edition Number: 1

  • Number of Pages: XI, 105

  • Number of Illustrations: 46 b/w illustrations, 35 illustrations in colour

  • Topics: Circuits and Systems, Electronic Circuits and Devices, Processor Architectures

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