Authors:
- Provides a comprehensive guide to the challenges and solutions for the testing of TSV-based 3D stacked ICs
- Includes in-depth explanation of key test and design-for-test technologies, emerging standards, and test- architecture and test-schedule optimizations
- Encompasses all aspects of test as related to 3D ICs, including pre-bond and post-bond test as well as the test optimization and scheduling necessary to ensure that 3D testing remains cost-effective
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Table of contents (9 chapters)
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Front Matter
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Back Matter
About this book
Authors and Affiliations
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ECE, Duke University, Durham, USA
Brandon Noia, Krishnendu Chakrabarty
About the authors
Bibliographic Information
Book Title: Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
Authors: Brandon Noia, Krishnendu Chakrabarty
DOI: https://doi.org/10.1007/978-3-319-02378-6
Publisher: Springer Cham
eBook Packages: Engineering, Engineering (R0)
Copyright Information: Springer International Publishing Switzerland 2014
Hardcover ISBN: 978-3-319-02377-9Published: 02 December 2013
Softcover ISBN: 978-3-319-34534-5Published: 23 August 2016
eBook ISBN: 978-3-319-02378-6Published: 19 November 2013
Edition Number: 1
Number of Pages: XVIII, 245
Number of Illustrations: 18 b/w illustrations, 115 illustrations in colour
Topics: Circuits and Systems, Processor Architectures, Semiconductors