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  • © 1982

The Architecture of High Performance Computers

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Table of contents (7 chapters)

  1. Front Matter

    Pages i-vii
  2. Introduction

    • Roland N. Ibbett
    Pages 1-6
  3. Instructions and Addresses

    • Roland N. Ibbett
    Pages 7-25
  4. Storage Hierarchies

    • Roland N. Ibbett
    Pages 26-48
  5. Pipelines

    • Roland N. Ibbett
    Pages 49-71
  6. Instruction Buffering

    • Roland N. Ibbett
    Pages 72-94
  7. Parallel Functional Units

    • Roland N. Ibbett
    Pages 95-125
  8. Vector Processes

    • Roland N. Ibbett
    Pages 126-164
  9. Back Matter

    Pages 165-172

About this book

Introduction 1. 1 Historical Developments 1 1. 2 Techniques for Improving Performance 2 1. 3 An Architectural Design Example 3 2 Instructions and Addresses 2. 1 Three-address Systems - The CDC 6600 and 7600 7 2. 2 Two-address Systems - The IBM System/360 and /370 10 2. 3 One-address Systems 12 2. 4 Zero-address Systems 15 2. 5 The MU5 Instruction Set 17 2. 6 Comparing Instruction Formats 22 3 Storage Hierarcbies 3. 1 Store Interleaving 26 3. 2 The Atlas Paging System 29 3. 3 IBM Cache Systems 33 3. 4 The MU5 Name Store 37 3. 5 Data Transfers in the MU5 Storage Hierarchy 44 4 Pipelines 4. 1 The MU5 Primary Operand Unit Pipeline 49 4. 2 Arithmetic Pipelines - The TI ASC 62 4. 3 The IBM System/360 Model 91 Common Data Bus 67 5 Instruction Buffering 5. 1 The IBM System/360 Model 195 Instruction Processor 72 5. 2 Instruction Buffering in CDC Computers 77 5. 3 The MU5 Instruction Buffer Unit 82 5. 4 The CRAY-1 Instruction Buffers 87 5. 5 Position of the Control Point 89 6 Parallel Functional Units 6. 1 The CDC 6600 Central Processor 95 6. 2 The CDC 7600 Central Processor 104 6. 3 Performance 110 6 • 4 The CRA Y-1 112 7 Vector Processors 7. 1 Vector Facilities in MU5 126 7. 2 String Operations in MU5 136 7. 3 The CDC Star-100 142 7. 4 The CDC CYBER 205 146 7.

Authors and Affiliations

  • Computer Science, University of Manchester, UK

    Roland N. Ibbett

Bibliographic Information

  • Book Title: The Architecture of High Performance Computers

  • Authors: Roland N. Ibbett

  • DOI: https://doi.org/10.1007/978-1-4757-6715-5

  • Publisher: Springer New York, NY

  • eBook Packages: Springer Book Archive

  • Copyright Information: Roland N. Ibbett 1982

  • Hardcover ISBN: 978-0-387-91215-8

  • Softcover ISBN: 978-1-4757-6717-9

  • eBook ISBN: 978-1-4757-6715-5

  • Edition Number: 1

  • Number of Pages: VII, 172

  • Topics: Computer Hardware

Buy it now

Buying options

eBook USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Other ways to access