Authors:
Part of the book series: The Springer International Series in Engineering and Computer Science (SECS, volume 501)
Buy it now
Buying options
Tax calculation will be finalised at checkout
Other ways to access
This is a preview of subscription content, log in via an institution to check for access.
Table of contents (7 chapters)
-
Front Matter
-
Back Matter
About this book
In the past, automatic analog layout tools tried to optimize the layout without quantifying the performance degradation introduced by layout parasitics. Therefore, it was not guaranteed that the resulting layout met the specifications and one or more layout iterations could be needed. In Analog Layout Generation for Performance and Manufacturability, the authors propose a performance driven layout strategy to overcome this problem. In this methodology, the layout tools are driven by performance constraints, such that the final layout, with parasitic effects, still satisfies the specifications of the circuit. The performance degradation associated with an intermediate layout solution is evaluated at runtime using predetermined sensitivities. In contrast with other performance driven layout methodologies, the tools proposed in this book operate directly on the performance constraints, without an intermediate parasitic constraint generation step. This approach makes a completeand sensible trade-off between the different layout alternatives possible at runtime and therefore eliminates the possible feedback route between constraint derivation, placement and layout extraction.
Besides its influence on the performance, layout also has a profound impact on the yield and testability of an analog circuit. In Analog Layout Generation for Performance and Manufacturability, the authors outline a new criterion to quantify the detectability of a fault and combine this with a yield model to evaluate the testability of an integrated circuit layout. They then integrate this technique with their performance driven routing algorithm to produce layouts that have optimal manufacturability while still meeting their performance specifications.
Analog Layout Generation for Performance and Manufacturability will be of interest to analog engineers, researchers and students.
Authors and Affiliations
-
Katholieke Universiteit Leuven, Belgium
Koen Lampaert, Georges Gielen, Willy Sansen
Bibliographic Information
Book Title: Analog Layout Generation for Performance and Manufacturability
Authors: Koen Lampaert, Georges Gielen, Willy Sansen
Series Title: The Springer International Series in Engineering and Computer Science
DOI: https://doi.org/10.1007/978-1-4757-4501-6
Publisher: Springer New York, NY
-
eBook Packages: Springer Book Archive
Copyright Information: Springer Science+Business Media New York 1999
Hardcover ISBN: 978-0-7923-8479-3Published: 30 April 1999
Softcover ISBN: 978-1-4419-5083-3Published: 09 December 2010
eBook ISBN: 978-1-4757-4501-6Published: 18 April 2013
Series ISSN: 0893-3405
Edition Number: 1
Number of Pages: XV, 175