VLSI Synthesis of DSP Kernels

1. Front Matter

   Pages i-xxiii

   PDF

2. Introduction

   • Manesh Mehendale, Sunil D. Sherlekar

   Pages 1-9

3. Programmable DSP Based Implementation

   • Manesh Mehendale, Sunil D. Sherlekar

   Pages 11-53

4. Implementation Using Hardware Multiplier(s) and Adder(s)

   • Manesh Mehendale, Sunil D. Sherlekar

   Pages 55-73

5. Distributed Arithmetic Based Implementation

   • Manesh Mehendale, Sunil D. Sherlekar

   Pages 75-111

6. Multiplier-Less Implementation

   • Manesh Mehendale, Sunil D. Sherlekar

   Pages 113-140

7. Implementation of Multiplication-Free Linear Transforms on a Programmable Processor

   • Manesh Mehendale, Sunil D. Sherlekar

   Pages 141-169

8. Residue Number System Based Implementation

   • Manesh Mehendale, Sunil D. Sherlekar

   Pages 171-185

9. A Framework for Algorithmic and Architectural Transformations

   • Manesh Mehendale, Sunil D. Sherlekar

   Pages 187-193

10. Summary

    • Manesh Mehendale, Sunil D. Sherlekar

    Pages 195-197

11. Back Matter

    Pages 199-209

    PDF

A critical step in the design of a DSP system is to identify for each of its components (DSP kernels) an implementation architecture that provides the desired degree of flexibility/programmability and optimises the area-delay-power parameters. The book covers the entire solution space comprising both hardware multiplier-based and multiplex-less architectures that offer varying degrees of programmability. For each of the implementation styles, several algorithmic and architectural transformations are proposed so as to optimally implement weighted-sum based DSP kernels over the area-display-power space.
VLSI Synthesis of DSP Kernels presents the following:

Six different target implementation styles -

• Programmable DSP-based implementation;
• Programmable processors with no dedicated hardware multiplier;
• Implementation using hardware multiplier(s) and adder(s);
• Distributed Arithmetic (DA)-based implementation;
• Residue Number System (RNS)-based implementation; and
• Multiplier-less implementation (using adders and shifters) for fixed coefficient DSP kernels.

For each of the implementation styles, description and analysis of several algorithmic and architectural transformations aimed at one or more of reduced area, higher performance and low power;

Automated and semi-automated techniques for applying each of these transformations; and

Classification of the transformations based on the properties that they exploit and their encapsulation in a design framework. A methodology that uses the framework to systematically explore the application of these transformations depending on the characteristics of the algorithm and the target implementation style.

VLSI Synthesis of DSP Kernels is essential reading for designers of both hardware- and software-based DSP systems, developers of IP modules for DSP applications, EDA tools developers, researchers and managers interested in getting a comprehensive overview of current trends and future challenges in optimal implementations of DSP kernels. It will also be suitable for graduate students specialising in the area of VLSI Digital Signal Processing.

• Hardware
• Signal
• VLSI
• algorithms
• architecture
• digital signal processor
• software
• tables

From the reviews:

"This book is devoted to describing the extremely fruitful ‘marriage’ between digital signal processing (DSP) and integrated circuit technology. … The present book is a generous and most qualified offer to all developers, either researchers or managers interested in VLSI and DSP, but especially to practicing system designers involved in both hardware and software optimal implementation of DSP kernels." (Neculai Curteanu, Zentralblatt MATH, Vol. 1050, 2005)

• Texas Instruments (India), Ltd., USA

  Manesh Mehendale

• Silicon Automation Systems Ltd., USA

  Sunil D. Sherlekar

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